We are using ADSP21992 with 12.96 MHz crystal connected to it for clock. We use on chip PLL to double it to approx 26 MHz.
It is working fine on 2-3 boards that we have for prototype.
Now, I came across this errata sheet which clearly says that for <40MHz, the PLL should not be used.
My question here is what kinds of problems occur?
1) Is it that one out of 1000 processors will have this issue and the PLL on that processor will never work?
2) The PLL may not work once per thousand start ups for the same processor.
Please let us know.
Thanks and regards,
I see that you have also submitted this same question to private support. To avoid duplication of effort, we will answer through that channel and post the outcome here.
We got the answer through private support.
It is the option 2) from my first post. So we will go for BYPASS mode.