Unable to boot TS-101 from linkport macro in FPGA


     I'm using a link macro in FPGA to boot TS-101.But it doesn't work.


     I'm doing all this on a custom board with two TS-101 on it,each has its own JTAG interface;  the two TS-101 have a linkport connect to each other,And also the two TS-101 each has a link port connect to FPGA ,  which use the xilinx linkport macro . 

     What I've done is :

           1.Use the FPGA macro to transmit data to ts-101 when using emulator to debug the other ts-101 ,which I have configured a link dma receive  with reg   L3CTL =   0x4C0, and it works.The data I received is good.

           2.Test the dxe file . I built up a project which can blink my led.and generate a ldr file with linkport 1(default one,and this is the linkport that  connect between the dsps directly.). And when I use this ldr to boot a TS-101 from the other, It works.

           3.So I changed the bootrom to linkport 3(this port is the one connect to dsp from macro in fpga).and send this new ldr from fpga to DSP. It cannot boot.(I've disconnect the emulator)

     So what should I do? How can I check the data that the TS101 received from linkport?(I've thought to configure halt only instead of halt and reset.)



  • 0
    •  Analog Employees 
    on Jan 16, 2013 7:05 AM

    Hi Silenuszhi,

                    I understand that you are trying to boot the ADSP-TS101 processor from FPGA using link port3. I can see that you have confirmed the link port interface working between FPGA and processor. Also the processor is able to boot from another processor using link port 1.

    I would suggest you to try the following for the FPGA boot test case:

    1. Make sure that there is no activity on the other link ports except link port 3. Since all the link ports are enabled when the processor is configured for link port booting any activity can affect the booting.

    2. You may also reduce the speed of the link port 3 and see whether it helps.

    3. After the boot failure connect the processor using the JTAG "Do not disturb" mode. This option lets you see the contents of the internal memory and registers without resetting the processor.

    If you can send more details about step 3, I will add more details later.

    Best Regards,


  • Hi Jeyanthi:

                   Thank you for your reply.

                   Actually,I can use the other processor's link3 to boot the first TS-101 from link3.

              So,according to ur suggestion,we did a test and the reg and memory content is as below:

    We use the link macro in fpga to send ldr file to ts101 from link3.Then with using do not disturb,we connect the emulator.It shows like processor is running ,so we halt the processor use shift+F5,and open the reg and memory.The result is in the 1st fig.

    next,we change the link boot rom,and revise the LCTL3 reg to 0x00000480 in the TS101_link.asm. The redo the process described before.The result is in fig 2.

    Meanwhile,when you say reduce the link speed , you mean decrease the CCLK or the FPGA CLK? I have use the CCLK/8.   btw, CCLK = 300MHz in my case.

    So what u suggest us to do next.Thank u!



  • 0
    •  Analog Employees 
    on Jan 25, 2013 1:47 PM

    Hi Silenuszhi,

                   Sorry for the delay again. Please confirm me on whether the boot kernel is getting downloaded correctly. If the first 256 instructions are downloaded correctly then you can add a jump loop instruction in the boot kernel and check. Once the boot kernel starts executing then you can connect using emulator in Do not disturb mode and single step by changing the jump loop to NOP instruction.

    If the boot kernel itself is not downloaded correctly then you can probe the link port signals to see what happens.

    In the earlier post I had asked the link port speed to be reduced to see whether it helps. You may also vary the combination of link port and CCLK speeds and see what happens.

    Best Regards,


  • I'm sorry that I forget to finish this discussion.Finally I boot ts-101 successfully. I've changed the speed of fpga to 60MHz and revise the ucf. And it works. Thank u  very much

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:48 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin