ts201

HI!

QUESTION 1:

I use TS201 IRQ0 interrupt, sometimes I find that when using the RTI out of the interrupt, the corresponding PMASK hasn't been cleared,SO the

programs cannot into the interrupt again.

QUESTION 2:

I use  link port of two DSP and

Procedures used were used to link two DSP  through the dedicated DMA channels to receive the same data from FPGA, in order to keep the synchronization of the receiving, I AND the two LXACKO signals as FPGA transmit enable signal, but the result is a DSP success, another DSP ONLY received a portion of the data.

THANK YOU




  • 0
    •  Analog Employees 
    on Feb 12, 2013 4:57 AM

    Hi,

       Sorry for the delay in getting back on your questions. Please see my answers as below:

    QUESTION 1:

    I use TS201 IRQ0 interrupt, sometimes I find that when using the RTI out of the interrupt, the corresponding PMASK hasn't been cleared,SO the

    programs cannot into the interrupt again.

    Ans >> It will be good if you can share the code which you have used for this testing.

    QUESTION 2:

    I use  link port of two DSP and

    Procedures used were used to link two DSP  through the dedicated DMA channels to receive the same data from FPGA, in order to keep the synchronization of the receiving, I AND the two LXACKO signals as FPGA transmit enable signal, but the result is a DSP success, another DSP ONLY received a portion of the data.

    Ans >> From the description I understand that the FPGA sends the data to link ports of two processors simultaneously. Since the link port communication depends on the handshake between transmitter and receiver I am not sure on whether ANDING the LxACKO signals will violate the timings needed for link ports. Have you verified on whether the link port communication works fine individually between the DSP's link port and FPGA for both the processors. If the problem happens only when both the processors are used simultaneously, can you probe the link port signals and see whether they look as expected.

    Since the same data is received by both the processors, you can think of the below approach:

    1. use one link port to receive the data and place it in common external memory or internal memory of the processor

    2. Use multiprocessor feature to inform the other link port once the transfer is completed. Or send the data using another link port to the other processor.

    Best Regards,

    Jeyanthi

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:46 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin