I've got a problem with simultaneous access to the external port and timer 0 interrupt. The timer interrupt period is 100 mks, the external port access is 100 ms. Timer0 works just like a counter to obtain 100 ms period and nothing else. The point is I try to read 10 bytes from the external port and if the timer interrupt occurs during read cycle time I've got one spurious read (11 read cycles), but in that case I have wrong buffer (without one byte). I disabled interrupts during read cycle and everything work properly. I use PFx as a chip select signal. What's the problem?
Thanks for help.
This issue was discussed through private support. I was able to reproduce the problem with the simpler test case having only one interrupt. It appears that interrupts must be disabled before processor makes access to external port.