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adsp-2191m Not Recommended for New Designs
The ADSP-2191 is a 160 MIPS 16-bit fixed point DSP that is software compatible with DSPs in the ADSP-218x family, noted for its easy-to-use algebraic assembly...
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adsp-2191m on Analog.com

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ADSP-2191M PLL stuck



		

			

									
					    Aveco
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 9, 2017 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    
 
    we have a system with ADSP-2191M that starts in bypass mode (BYPASS pin unconnected). After successful start the program sets PLLCNTL to required multiplication factor (CLKIN=40MHz, multiplier=4x to achieve 160MHz CCLK) and switches CCLK to be driven from PLL, ie. deactivates bypass mode. From this time the processor stops executing its program. Processor reset does not help in this case, ie. after another reset the program running fine while in bypass mode but stops as soon as bypass deactivated again. Power down and up the board will sometimes help (ie. the program is running fine even after bypass mode deactivated), sometimes does not. We have hundreds of boards running fine but the last series suffers from this problem. Do you have some hint what we can check, please, that could cause PLL is unusable?
    
 
    Thank you,
    
 
    Michal
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ADSP-2191M
                
                                                    
                 processors and dsp
                
                                                    
                 ADSP-21xx Fixed-Point DSPs
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2017 6:15 AM
            
            
					
      
	
      

		
		
      
					
      Hi Michal,
      
 
       I am not sure whether you are still looking into this, The problem appears to be associated with either PLL programming issue or reset sequencing issue.
      
 
       When PLL is programmed out of bypass mode, the core should wait for at least 500 clkin cycles, Is this properly taken care in your application.
      
 
       After CLKIN has been stabilized, reset should be low for atleast 200 CLKIN cycles for proper reset.
      
 
       If CLKOUT pin is available in your system, can you please probe clock out, it will atleast give you some ideas about PLL's stability.
      
 
      Thanks,
      
 
      Sachin 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2017 6:15 AM
            
            
					
      
	
      

		
		
      
					
      Hi Michal,
      
 
       I am not sure whether you are still looking into this, The problem appears to be associated with either PLL programming issue or reset sequencing issue.
      
 
       When PLL is programmed out of bypass mode, the core should wait for at least 500 clkin cycles, Is this properly taken care in your application.
      
 
       After CLKIN has been stabilized, reset should be low for atleast 200 CLKIN cycles for proper reset.
      
 
       If CLKOUT pin is available in your system, can you please probe clock out, it will atleast give you some ideas about PLL's stability.
      
 
      Thanks,
      
 
      Sachin 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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