ADSP-2191M PLL stuck

Hi Michal,

 I am not sure whether you are still looking into this, The problem appears to be associated with either PLL programming issue or reset sequencing issue.

 When PLL is programmed out of bypass mode, the core should wait for at least 500 clkin cycles, Is this properly taken care in your application.

 After CLKIN has been stabilized, reset should be low for atleast 200 CLKIN cycles for proper reset.

 If CLKOUT pin is available in your system, can you please probe clock out, it will atleast give you some ideas about PLL's stability.

Thanks,

Sachin 

Hi Sachin,

the code I use to program PLL follows recommendation of EE-153. I also tried to add much longer wait loops but without success.

As the ADSP is placed on PCI card, it takes many seconds before the ADSP reset is deasserted so CLKIN is stable at that time. Also CLKOUT refers to CLKIN while in BYPASS but stops as soon as the core clock is switched to PLL output.

The problem seems to be related to initial power up sequence. We have found out that the PLL works well if VDD slew rate is slow enough. As mentioned before if PLL does not work, assert/deassertion of reset signal will not help, only power cycle can help.

Best regards,

Michal

Hi Aveco,

 I am in touch with internal product team, I will get back to you as soon as possible.

Thanks,

Sachin