Post Go back to editing

Can I access TigerSharc DSP processor directly with PC without glueless interfacing to FPGA?


I am working on designing of a test board which involves both FPGA(Xilinx- Kintex 7) and DSP(Tiger Sharc) based signal processing. Now the end user wants to access the DSP processor programming options/ boot configuration through the host PC itself. As I went through the datasheets of these devices I got the idea that I'll have to use PPLP for the communication purposes with FPGA. My question is that- Is there any device or connector which supports communication for DSP processor with host PC Such as PPLP to USB(- Is this a good idea to use)? My current goal of the system design is to implement any way to directly access the chain of DSPs from host PC apart from the FPGA since it causing a bit of delay. I am looking for any device or IC which could drive the communication with DSPs' link port to any suitable protocol of PC (Could be UART, USB, ethernet anything which can communicate with PC since PCs don't have link port access...)- much like FTDI2232 which drives USB to UART\FIFO.

Would really appreciate if anyone has any good and concise idea about this kind of devices.



  • Hi Mandan,

                I apologize for the delay in getting back here. I cannot think of any connector which will allow the connection between Host PC and TigerSHARC DSP. I would like to check with you on whether the TigerSHARC and FPGA are connected on the board. If yes, then you can use the FPGA to talk to the host and it can control the TigerSHARC based on the inputs from Host. I could not provide more inputs without knowing exactly how the board is designed.

    Best Regards,


  • Hi Jeyanthi,

    Thanks for your response!

    As for now I am using the Link Port connection with FPGA and controlling it from there with host PC.

    I had another doubt regarding power sequencing for this processor. Should I follow the power sequencing as mentioned in the eval board for this processor or would it be better to go for proper sequencing(Core voltage supply first, then IO supply and then VDDRAM; maybe using any TI regulators and sequencers as we do in FPGAs)?
    Also, I am using multiprocessor design(3 DSP), so is it okay to supply the core 1.2V with a single ADP 1821 regulator for all 3 DSPs(max draw load current would be 8.7A) or should I go for separate regulators for individual DSPs?
    My area of concern is- will a single controller be able to supply this much of current for core 1.2V without any problem(In the datasheet it is mentioned 1.8V @ 20A, but there is no efficiency graphs for 1.2V).

    Thanks Again,

  • Hi Mandan,

                 Please follow the Datasheet recommendations for the power-up sequencing here.



  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin