ADuCM360 wrong timer period.

ADuCM360 wrong timer period.

I am trying to implement signal generator on ADuCM360 using DAC+DMA with TIMER1 as DMA activation source. The microcontroller is running on 16 MHz, timer is configured for PCLK as source clock and divider 1. DMA is working with 64 values and I monitor the DMA interrupt for timing.

The first problem is that the timer clock seems to be prescaled by factor of 4 even if I use PCLK and prescaler 1.

The second problem is: with time LD value of 7 I should get timer interval of 1.75 microseconds (with prescaler of 4) which should after 64 activation of DMA transfer trigger the DMA interrupt with interval of 112 microseconds. But I observe 127.2 microseconds. The direct timer interrupt monitoring also demonstrates large difference in measured interval for low LD values.

So question is if I am missing something here or how this behavior can be explained.

Thank you

Victor

  • 0
    •  Analog Employees 
    on Apr 18, 2018 11:24 AM

    Hi Victor,

    Firstly the frequency of PCLK is related with the bit0 of CLKSYSDIV register and the bit[2:0] of the CLKCON0 register. Please make sure of it.

    The timer clock is also related with the bit0 of CLKSYSDIV register and the timer related register. The timer example code is available on the ftp://ftp.analog.com/pub/MicroConverter/ADuCMxxxV1.3/

    You can download the ADUCMxxxV1.3.exe file and install it. Then you can find the example code. It should can help you to understand the clock frequency of PCLK and timer clock.

    The timer interval depends on the selected clock source and timer configuration (up/down counter, value) besides timer clock. Please share more information.

    If you use the 32.768kHz as the timer clock, please note that the tolerance of the 32.768kHz.

    Regards,

    Barry

  •   Hi Barry,

      Than you for replay.

      My code (relevant part of it) is below:

    void
    GP_Tmr1_Int_Handler(void)
    {
      pADI_GP2->GPOUT = 0x01;
      pADI_TM1->CLRI = T0CLRI_TMOUT_CLR;
      pADI_GP2->GPOUT = 0x00;

    }

    int
    main (void) {

      pADI_WDT->T3CON = 0;
      pADI_CLKCTL->CLKCON0 = CLKCON0_CLKOUT_PCLK | CLKCON0_CLKMUX_HFOSC | CLKCON0_CD_DIV1;
      pADI_CLKCTL->CLKSYSDIV = 0x0; // CLKSYSDIV_DIV2EN_DIS; // No divide of 16MHz system clock
      pADI_CLKCTL->CLKCON1 = 0x0; // PWM = 16MHz, UART = 16MHz, SPI1 = 16MHz, SPI0=16MHz
      pADI_CLKCTL->CLKDIS = 0x0; // Enable clock to all peripherals
      pADI_CLKCTL->XOSCCON = 0x0; // XOSCCON_ENABLE_DIS | XOSCCON_DIV2_DIS;
    #if 1
      pADI_GP0->GPCON |= 0x200; // CLKOUT
      pADI_GP0->GPOEN = GPOEN_OEN4_OUT;
    #endif

      pADI_TM1->CON = T1CON_ENABLE_DIS;
      pADI_TM1->LD = 16;
      pADI_TM1->CON = T1CON_CLK_PCLK | T1CON_ENABLE | T1CON_MOD_PERIODIC | T1CON_UP_DIS | T1CON_PRE_DIV1;

      ISER0 |= ISER0_T1_EN;

      for (;;) {
        __NOP();
        __WFI();
      }

    }

      I control the PCLK on P0.4 pin (it is correct - 16 MHz), interrupt is traced on P2.1. The P2.1 output is measured to be 4.224 uS / 236.7 kHz instead of calculated 1 MHz, and the PCLK counts between two interrupt pulses is 68, which is not even a multiply of 16 (pADI_TM1->LD)

      Regards,

      Victor

  • 0
    •  Analog Employees 
    on Apr 19, 2018 8:59 AM

    Hi Victor,

    Perhaps the reason is that the GPIO cannot toggle up to the frequency 1MHz. Also the related instructions need time to execute. please have a try to toggle the P2.1 of the frequency starting from 100kHz. If everything is ok, then increase the GPIO toggle frequency.

    Regards,

    Barry