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EEPROM boot in ADSP-TS201 multiprocessor configuration

Category: Software

ADSP-TS201 I have a question about EEPROM boot in a multiprocessor configuration.

I'm trying to understand the boot sequence for a multiprocessor configuration by comparing the ADSP-TS201 datasheet,

the TigerShark architecture AP, EE and the files in his Example project for Visual DSP 5.1.2.

I don't have a board to check the operation.

However, it is a situation where you need to understand the detailed operation sequence.

I want to know.

For multiprocessors

1. Will the next priority DSP of ID01 load the boot kernel from FLASH as well as the DSP of ID00 after ID00’s DSP boots?

2. Which address in the DSP internal memory is the boot kernel loaded after booting?

3. How to specify the boot kernel load address in the ldf file?

The background of this question is as follows.

I checked some documents as mentioned above and found the following description.

"When EPROM boot mode is selected, the ADSP TS20x processor initializes its external port DMA channel 0 to transfer 256 32-bit words of code

from the boot EPROM into memory block 0 locations 0x00-0xFF of the ADSP-TS20x processor. "

I understood that this "256 32-bit words" is the boot kernel.

And I found that there is a description in "VISUAL DSP ++ 5.0 Loader and Utilities Manual"

about how to load the boot kernel to any address in the DSP internal memory.

The description is as follows.

"A boot kernel is loaded at reset into a memory segment, seg_ldr, which is defined in the ADSP TSxxx_Loader.ldf file."

However, when I check the example multiprocessor ldf file that exists in the folder of VisualDSP 5.1.2, I cannot find the description of seg_ldr.

I checked the following files.

"VisualDSP 5.1.2 \ TS \ Examples \ ADSP-TS201 EZ-KIT Lite \ AudioPassThrough C \ ADSP-TS201_C_MP.ldf"

    M0Code      { TYPE(RAM) START(0x00000000) END(0x0001FF9F) WIDTH(32) }
    M2DataA     { TYPE(RAM) START(0x00040000) END(0x0004FFFF) WIDTH(32) }
    M2DataB     { TYPE(RAM) START(0x00050000) END(0x0005FFFF) WIDTH(32) }
    M4DataA     { TYPE(RAM) START(0x00080000) END(0x0008FFFF) WIDTH(32) }
    M4DataB     { TYPE(RAM) START(0x00090000) END(0x0009BFFF) WIDTH(32) }
    M4Heap      { TYPE(RAM) START(0x0009C000) END(0x0009C7FF) WIDTH(32) }
    M4Stack     { TYPE(RAM) START(0x0009C800) END(0x0009FFFF) WIDTH(32) }
    M6DataA     { TYPE(RAM) START(0x000C0000) END(0x000CFFFF) WIDTH(32) }
    M6DataB     { TYPE(RAM) START(0x000D0000) END(0x000DC7FF) WIDTH(32) }
    M6Stack     { TYPE(RAM) START(0x000DC800) END(0x000DFFFF) WIDTH(32) }
    M8DataA     { TYPE(RAM) START(0x00100000) END(0x0010FFFF) WIDTH(32) }
    M8DataB     { TYPE(RAM) START(0x00110000) END(0x0011FFFF) WIDTH(32) }
    M10DataA     { TYPE(RAM) START(0x00140000) END(0x0014FFFF) WIDTH(32) }
    M10DataB     { TYPE(RAM) START(0x00150000) END(0x0015FFFF) WIDTH(32) }

    MS0         { TYPE(RAM) START(0x30000000) END(0x37FFFFFF) WIDTH(32) }
    MS1         { TYPE(RAM) START(0x38000000) END(0x3FFFFFFF) WIDTH(32) }
    MSSD0       { TYPE(RAM) START(0x40000000) END(0x43FFFFFF) WIDTH(32) }
    MSSD1       { TYPE(RAM) START(0x50000000) END(0x53FFFFFF) WIDTH(32) }
    MSSD2       { TYPE(RAM) START(0x60000000) END(0x63FFFFFF) WIDTH(32) }
    MSSD3       { TYPE(RAM) START(0x70000000) END(0x73FFFFFF) WIDTH(32) }

// Memory blocks need to be less than 2 Gig.
     HOST        { TYPE(RAM) START(0x80000000) END(0x8FFFFFFF) WIDTH(32) }
    HOST1       { TYPE(RAM) START(0x90000000) END(0xAFFFFFFF) WIDTH(32) }
    HOST2       { TYPE(RAM) START(0xB0000000) END(0xCFFFFFFF) WIDTH(32) }
    HOST3       { TYPE(RAM) START(0xD0000000) END(0xEFFFFFFF) WIDTH(32) }
    HOST4       { TYPE(RAM) START(0xF0000000) END(0xFFFFFFFF) WIDTH(32) }

At what address is the boot kernel loaded in this example?
Will it be loaded into his address in M0Code?
If so, I don't understand why the END address is 0x0001FF9F.
I expected him to be 0x000000FF. And I'm confused.
I was so confused.

I'm sorry, begging for help.

Best regards.


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