TS201S internal bus arbitration between core (read) and DMA (write from Link port)


I would like to know TS-201S internal bus arbitration especially between core read and DMA write.

DMA transfer data from LinkPort into the memory. DSP core try to read same address but read old data that mean before DMA complete transfer from LinkPort  into that memory.

So try to adjust DSP core read timing and DMA transfer timing are not same time. But still these timings are same but some times DSP core read proper value, other time DSP core read not correct value (that mean old value before DMA completed transfer).

I would like to appreciate it for your sharing any document that described such a internal data bus arbitration architecture or give me advice how DSP core know DMA transfer completed. (using interrupt or poring such kind of register value by CPU)

Thank you for your help.

Best regards,