Memory restriction in Core0(ARM) ADSPSC58x

where we need to check these memory restrictions on core0(ARM Cortex-A5)ADSPSC58x.

According to the processor reference manual i found these below sizes.

Please clarify this doubt?

>Core0 Dedicated L1 - 64KB?!(Memory Size)
>Core0 Dedicated L2 - 256KB?!(Memory Size)
>Common L2
>Common L3

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  • HI Jithul,

    Thanks for your continues support.

    Please clarify these below quires.

    1. Figure_5 they given ARM address space range 0x00000000 to 0x20000000.But in .map file starting address 0x00000000,0x20008000 and 0x89000000 range available.

    2. Figure_1:32KB Instruction cache and 32KB Data cache. Where we need to check these memory range.

    3. Please provide Core0 L2 memory address ranges start and end address.

Reply
  • HI Jithul,

    Thanks for your continues support.

    Please clarify these below quires.

    1. Figure_5 they given ARM address space range 0x00000000 to 0x20000000.But in .map file starting address 0x00000000,0x20008000 and 0x89000000 range available.

    2. Figure_1:32KB Instruction cache and 32KB Data cache. Where we need to check these memory range.

    3. Please provide Core0 L2 memory address ranges start and end address.

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