Memory restriction in Core0(ARM) ADSPSC58x

where we need to check these memory restrictions on core0(ARM Cortex-A5)ADSPSC58x.

According to the processor reference manual i found these below sizes.

Please clarify this doubt?

>Core0 Dedicated L1 - 64KB?!(Memory Size)
>Core0 Dedicated L2 - 256KB?!(Memory Size)
>Common L2
>Common L3

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  • Hi Jithul,
    Thanks for your continues support.

    In Core_0 adsp-sc58x-common.ld file L1 memory not present.L2 and L3 memory only available on Core0 .ld file.
    In reference manual Figure-1 L1-Cache (32KB-Instruction cache,32KB-Data Cache) available.
    where we need to check this L1 cache memory on Core0 and L2 Cache memory in document wise 256KB given at Figure_1.

    Please provide where this cache  memories available.


    Please provide the feedback.

Reply
  • Hi Jithul,
    Thanks for your continues support.

    In Core_0 adsp-sc58x-common.ld file L1 memory not present.L2 and L3 memory only available on Core0 .ld file.
    In reference manual Figure-1 L1-Cache (32KB-Instruction cache,32KB-Data Cache) available.
    where we need to check this L1 cache memory on Core0 and L2 Cache memory in document wise 256KB given at Figure_1.

    Please provide where this cache  memories available.


    Please provide the feedback.

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