The ADAU1452 and ADAU1463 data sheets mention automatic dejitter for the clock generator, and also specify that CLKOUT has anywhere from 12 ps to 206 ps of jitter.
I am curious about the performance of the dejitter function, and where it is effective.
A) How much can the dejitter correct? Is there a range of allowed jitter on the MCLK input that can be corrected? ... or is there a limit to the dejitter performance?
B) It appears from the diagrams that dejitter is certainly applied to the clock generators for the serial ports, but it's unclear whether dejitter also improves the CLKOUT quality.
i.e. Is CLKOUT jitter of 12 to 206 ps guaranteed no matter what jitter MCLK has?
C) Assuming dejitter is automatic for all serial port clocks, what is the jitter range there? (I am assuming it may be different from the provided specifications for CLKOUT)
I have designed a board with the ADAU1463 and two AD2437 chips, with the ability to switch MCLK on the SigmaDSP from either a low-jitter oscillator or the CLKOUT2 signal from the primary A2B chip. I'm curious how much the low-jitter oscillator actually helps when the ADAU1463 is master, and how much worse the jitter might be when taking the CLKOUT2 from A2B to MCLK.
