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I am not able to set the PLL CTL and PLL DIV Register- ADSP BF548 custom board.

Category: Software
Product Number: : ADSP-BF548, silicon 0.4
Software Version: visual dsp++5.1.2.0

i am current working on ADSP BF548 custom board, I am able to set the PLL CTL and PLL DIV Register. However, I am unable to check the SCLK values in my code; is there a way to do so? I've attached my code for reference.
Please assist me since I too want to write code for the spi protocol.


ADI_SYSCTRL_VALUES sys_cntrl_write;
ADI_SYSCTRL_VALUES sys_cntrl_read;

// Set CCLK = 400 MHz, SCLK = 133 MHz, voltage to 1.25v
sys_cntrl_write.uwPllCtl = 0x2000;
sys_cntrl_write.uwPllDiv = 0x0003;
sys_cntrl_write.uwVrCtl = 0x40EB;

bfrom_SysControl ( SYSCTRL_READ | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV |
SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &sys_cntrl_read, NULL );

printf("Before Set PLLCLT Reg : 0X%X\n",sys_cntrl_read.uwPllCtl);
printf("Before Set PLLDIV Reg : 0X%X\n",sys_cntrl_read.uwPllDiv);
printf("Before Set VRCTL Reg : 0X%X\n",sys_cntrl_read.uwVrCtl);

bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV |
SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &sys_cntrl_write, NULL);

bfrom_SysControl ( SYSCTRL_READ | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV |
SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &sys_cntrl_read, NULL );

printf("After Set PLLCLT Reg : 0X%X\n",sys_cntrl_read.uwPllCtl);
printf("After Set PLLDIV Reg : 0X%X\n",sys_cntrl_read.uwPllDiv);
printf("After Set VRCTL Reg : 0X%X\n",sys_cntrl_read.uwVrCtl);

results from the board : 

Parents
  • Hi,

    User-programmable value divides the VCO signal to generate the system clock (SCLK). You can calculate SCLK by using below formula SCLK = VCO/PLL_DIV.SSEL

    VCO is calculated by VCO = (SYS_CLKIN frequency/(DF+1)) MSEL. Please refer " 18 DYNAMIC POWER MANAGEMENT " in below linked HRM:www.analog.com/.../ADSP-BF54x_hwr_rev1.2.pdf

    Attached SPI transmission and reception example for BF592 across 2 EZkits. You can refer this for BF548.
    SPI_ADSP-BF592.zip
    Regards,
    Divya,P

  • Following your advice, I am now able to set the PLL registers. I have configured the board with the standard UART protocol which works as expected.
    Thank you for your help...

    Now I need to configure the PORTB register pins (PB9, PB12, PB13, PB14) as GPIO output pins and I want to see the high/low control of these pins, but the code I have provided below has no outputs. This code is based on the ADSPBF-548 datasheet.


    *pPORTB = PB9 | PB12 |PB13 | PB14; // GPIO Pin high

    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<9); 
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<12); 
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<13);
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<14); 

    *pPORTB_FER = PB12 | PB13 | PB14;//Enable pins
    ssync();

    (*pPORTB_MUX) = (*pPORTB_MUX) & ~(1<<18); // chip select 1
    (*pPORTB_MUX) = (*pPORTB_MUX) & ~(1<<19); // chip select 1


    My request is please help me too figure it out, how to configure these pins as GPIO or tell me what I am doing wrong to configure it.
    If you have any articles or examples on this please let me know.

Reply
  • Following your advice, I am now able to set the PLL registers. I have configured the board with the standard UART protocol which works as expected.
    Thank you for your help...

    Now I need to configure the PORTB register pins (PB9, PB12, PB13, PB14) as GPIO output pins and I want to see the high/low control of these pins, but the code I have provided below has no outputs. This code is based on the ADSPBF-548 datasheet.


    *pPORTB = PB9 | PB12 |PB13 | PB14; // GPIO Pin high

    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<9); 
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<12); 
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<13);
    (*pPORTB_FER) = (*pPORTB_FER) & ~(1<<14); 

    *pPORTB_FER = PB12 | PB13 | PB14;//Enable pins
    ssync();

    (*pPORTB_MUX) = (*pPORTB_MUX) & ~(1<<18); // chip select 1
    (*pPORTB_MUX) = (*pPORTB_MUX) & ~(1<<19); // chip select 1


    My request is please help me too figure it out, how to configure these pins as GPIO or tell me what I am doing wrong to configure it.
    If you have any articles or examples on this please let me know.

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