Dear Dave, I hope that you are doing well.
I have a problem on the outputs from ADAU 1772. i have one Digital PDM Microphone connected and operating at MCLK/4 =3.072 Mhz Clock normally , getting its clock output from MP6. The Core clock is set ( 1 Selected from divider) , Main Clock / 1 (1 selected from divider), output clock ( MCLK/4 )=3.072Mhz) . Our DSP Schematic objects are all set at 192 Khz Sample rate. With this configuration we have digital noise and cracks coming out of the outputs around 60K -150K Hz.
In our design we have IIr filters all set to work with 192 Khz sample rate and coefficients loaded according to this sample rate, therefore we have suceeded to eliminate this output noise by tuning the frequency on the tab PLL & Control Clock Section , with 12.288 Mhz clock crystal oscillator input , Core clock ( 1 Selected from divider) , Main Clock / 2 (2 selected from divider), output clock ( MCLK/6 )=6.144 Mhz) . This change helped us to get rid of the noises on the output but we had another challange appeared. The Eq objects in the design have shifted half of the center frequencies. When we move 100 Hz in eq , it affects 50 Hz in the output.
Which settings should we make in the configuration to run with 192 Khz sampling frequency and without any noise at the output?
Thank you in advance..