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SPORT DMA access to short Memory space

Category: Hardware
Product Number: ADSP21489


I am confused about  "Standard DMA Parameter Registers" on page 3-4  of 214xx HRM. Can someone give me a detailed explanation of:

1. HRM says index registes are 18 bit wide and have a fixed "1" at bit 19. This result in 19 bits. BUT as bits usualy starts with bit 0
a 18 bit wide register have bit 0 to bit 17.  What ist about bit 18 ?. The ADSP21489 needs 20 bits (bit 0 to bit 19) to address the
complete normal word space.

2. I am not sure about the offset (bit 19)  concering SPORT DMA index registers:
In case of a SPORT DMA, is the offset newer applicable (neither internal nor external memory) , or is it only related to internal memory ?

3. I have a running application with SPORT DMA buffer in normal word space. This works fine. As theSPORT receives only
16 Bit Samples, I changed the buffer to short memory space.  This didn't work, the buffer receives nothing. Should the
SPORT DMA be able to transfer 16 bit samples to short memory space ?

Best regrads
Peter Pfeiffer

  • Hi,

    All addresses in the index registers are offset by a value matching the processor’s first internal normal word addressed RAM location, before the I/O processor uses the addresses.
     For the ADSP-214xx processors, this offset value is 0x0008 0000. This internal memory offset is not applicable for the index registers that correspond to SPORT DMAs as these registers are
    28 bits.

    We recommend to refer "Table 3-2. Index Registers" in the ADSP-214xx HRM.
    Generally, the variable declared uses 32 bits in the SHARC, and there is no direct option to declare a 16 bit. For the memory optimization you can make use of packing/unpacking mechanism that is associated with the peripherals.  For instance, in SPORT peripheral, received data words of 16 bits or less may be packed into 32-bit words, and transmitted 32-bit words may be unpacked into 16-bit words. Word packing and unpacking is selected by the PACK bit in the SPCTLx control registers.

    Anand Selvaraj.