What are the Peripheral IDs associated with the 4 DMAs?

Hi Steve,

System protection unit(SPU) is used to protect the DMA channels. If you transfer the data through DMA channel, you should protect the appropriate DMA channel in the DMA controller. Please refer the System Protection Unit chapter in ADSP-2156x hardware reference manual.

You can find the SPU ID for DMA channels in ADSP-2156x hardware reference manual > System Protection Unit chapter > Write-Protect Register and Secure Peripheral Number(n)

Below are SPU ID's for MDMA channels:
MDMA0
Source ID  ->110
Destination ID  -> 111

MDMA1
Source ID ->112
Destination ID  ->113

Hope this helps.

Best Regards,
Santhakumari.K

Hi Santhatkumari.K,

There are 4 Memory DMA Streams available for the ADSP-2156 processor.

typedef enum
{
ADI_DMA_MEMDMA_S0, /*!< Memory DMA Stream 0 */
ADI_DMA_MEMDMA_S1, /*!< Memory DMA Stream 1 */
ADI_DMA_MEMDMA_S2, /*!< Memory DMA Stream 2 */
ADI_DMA_MEMDMA_S3, /*!< Memory DMA Stream 3 */
ADI_DMA_MEMDMA_END_COUNT /* Number of Memory DMA Streams */
} ADI_DMA_STREAM_ID;

Do you happen to know the SPU ID's for MDMA channels 2 and 3?

Thanks,

-Steve

Hi Santhakumari.K,

The MemCopyArrayMode_21569 example fails when changing the MEMCOPY_STREAM_ID to use  ADI_DMA_MEMDMA_S2 or ADI_DMA_MEMDMA_S3.

Are these DMA channels available?

-Steve

Hi Steve,

MDMA2 & 3 DMA channels are available.

MDMA2(Enhanced BW MDMA)
Source ID, Destination ID 101

MDMA3(Max BW MDMA)
Source ID, Destination ID 102

For MDMA 2 and 3, both source and destination SPU IDs are same.

Can you please try and let us know how you are getting on.

Best Regards,

Santhakumari.K

Hi Santhakumari.K,

The MemCopyArrayMode_21569 example does not have SPU enabled.  It fails when changing the MEMCOPY_STREAM_ID to use  ADI_DMA_MEMDMA_S2 or ADI_DMA_MEMDMA_S3.

Is there some additional system configuration required to access DMA 2 and 3?

I also added the SPU IDs to my app that has SPU enabled and the DMA fails as well.

-Steve

Hi Santhakumari.K,

After further investigation using all 4 DMAs is not a viable solution for our Paradigm.  Thank you for your assistance.

-Steve

Hi Santhakumari.K,

I modified a simple DMA0 example for DMA1.  I am not able to get the DMA1 interrupts. using DMAs 10/11 and Secure PID 112 = 0x3 and Secure PID 113 = 0x3.

From the documentation, these seem like valid values for DMA1.

Can  you verify?

volatile int DMA_Completed0 = 0;
volatile int DMA_Completed1 = 0;
void MDMA0_Write(uint8_t * pReadAddress, uint8_t * pWriteAddress, uint32_t iXCount);
void MDMA_Completion_ISR0(void);
void MDMA1_Write(uint8_t * pReadAddress, uint8_t * pWriteAddress, uint32_t iXCount);
void MDMA_Completion_ISR1(void);

adi_int_InstallHandler(INTR_SYS_MDMA1_DST,MDMA_Completion_ISR1,0,true);
adi_int_InstallHandler(INTR_SYS_MDMA0_DST,MDMA_Completion_ISR0,0,true);

void MDMA0_Write(uint8_t * pReadAddress, uint8_t * pWriteAddress, uint32_t iXCount)
{
//Configure MDMA0 Source and Destination channels as secure masters
*pREG_SPU0_SECUREP110 =0x3;
*pREG_SPU0_SECUREP111 =0x3;
// MDMA0 uses DMA channel 8 and 9 on GUL
*pREG_DMA8_CFG = 0;
*pREG_DMA9_CFG = 0;

*pREG_DMA8_ADDRSTART = (uint32_t *)pReadAddress; //Initialize start address
*pREG_DMA8_XCNT = iXCount; //Initialize X count
*pREG_DMA8_XMOD = 1; //Initialize DMA X modifier
*pREG_DMA8_YCNT = 0; //Initialize Y count
*pREG_DMA8_YMOD = 0; //Initialize DMA Y modifier

*pREG_DMA9_ADDRSTART = (uint32_t *)pWriteAddress; //Initialize start address
*pREG_DMA9_XCNT = iXCount; //Initialize DMA X count
*pREG_DMA9_XMOD = 1; //Initialize DMA X modifier
*pREG_DMA9_YCNT = 0; //Initialize DMA Y count
*pREG_DMA9_YMOD = 0; //Initialize DMA Y modifier

*pREG_DMA9_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_PSIZE01 |ENUM_DMA_CFG_MSIZE01 |ENUM_DMA_CFG_WRITE | ENUM_DMA_CFG_XCNT_INT; //Initialize DMA config register
*pREG_DMA8_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_PSIZE01 |ENUM_DMA_CFG_MSIZE01;//Initialize DMA config register

}

void MDMA1_Write(uint8_t * pReadAddress, uint8_t * pWriteAddress, uint32_t iXCount)
{
//Configure MDMA1 Source and Destination channels as secure masters
*pREG_SPU0_SECUREP112 =0x3;
*pREG_SPU0_SECUREP113 =0x3;

// MDMA0 uses DMA channel 10 and 11 on GUL
*pREG_DMA10_CFG = 0;
*pREG_DMA11_CFG = 0;

*pREG_DMA10_ADDRSTART = (uint32_t *)pReadAddress; //Initialize start address
*pREG_DMA10_XCNT = iXCount; //Initialize X count
*pREG_DMA10_XMOD = 1; //Initialize DMA X modifier
*pREG_DMA10_YCNT = 0; //Initialize Y count
*pREG_DMA10_YMOD = 0; //Initialize DMA Y modifier

*pREG_DMA11_ADDRSTART = (uint32_t *)pWriteAddress; //Initialize start address
*pREG_DMA11_XCNT = iXCount; //Initialize DMA X count
*pREG_DMA11_XMOD = 1; //Initialize DMA X modifier
*pREG_DMA11_YCNT = 0; //Initialize DMA Y count
*pREG_DMA11_YMOD = 0; //Initialize DMA Y modifier

*pREG_DMA11_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_PSIZE01 |ENUM_DMA_CFG_MSIZE01 |ENUM_DMA_CFG_WRITE | ENUM_DMA_CFG_XCNT_INT; //Initialize DMA config register
*pREG_DMA10_CFG = ENUM_DMA_CFG_EN | ENUM_DMA_CFG_PSIZE01 |ENUM_DMA_CFG_MSIZE01;//Initialize DMA config register

}
void MDMA_Completion_ISR0(void)
{
*pREG_DMA9_STAT |= 0x1;
DMA_Completed0 = 1;
}

void MDMA_Completion_ISR1(void)
{
*pREG_DMA11_STAT |= 0x1;
DMA_Completed1 = 1;
}

Thanks,

-Steve

The  sweep test has a simple macro with the DMA addresses hard coded to 8 and 9 for DMA 0.

What values would be expected for DMA 1, 10 and 11 do not work?

void MdmaAccess(uint32_t uiSourceDMACFG,uint8_t* pSrcBuf,uint32_t uiSourceMSIZE,uint32_t uiBuffSize1,
uint32_t uiDestDMACFG, uint8_t* pDestBuff, uint32_t uiDestMSIZE,uint32_t uiBuffSize2)
{
MDMA_CONFIG(8,uiSourceDMACFG, (uint8_t*)adi_rtl_internal_to_system_addr((uint32_t)pSrcBuf,0), uiSourceMSIZE, uiBuffSize1,9,uiDestDMACFG, (uint8_t*)adi_rtl_internal_to_system_addr((uint32_t)pDestBuff,0), uiDestMSIZE, uiBuffSize2);
WAIT_FOR_DMADONE(9);
DISABLE_MDMA(8,9);
}

Thanks,

-Steve

Hi Steve,

The DMA channels can perform transfers between memory and a peripheral or between one memory and another memory. For Memory-to-memory DMA transfers (MDMA) have a separate DMA channels. MDMA require two DMA channels. One channel is the source channel, and the second is the destination channel.

MDMA Channel    SOURCE DMA    DESTINATION DMA
MDMA 0                         DMA8                 DMA9
MDMA 1                         DMA18               DMA19
MDMA 2                         DMA39               DMA40
MDMA 3                         DMA43               DMA44


We suggest to refer the Table 27-2 ADSP-2156x DMA Channel List(Page No: 1239/2331). The link for the ADSP-21569 Hardware reference manual is given below.
www.analog.com/.../adsp-2156x_hwr.pdf

Please refer the attached project which transfers data using MDMA1.
ADSP_21569_MDMA1.zip

Regards,
Divya.P

Divya.P,

Thanks for the assistance.  The information and the example were very helpful.  

-Steve