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FrameSyncError (ADSP-21569)

Category: Hardware
Product Number: ADSP-21569

Dear sir,


Could you tell me the mechanism and cause of Frame Sync Error of SPORTs?

And, What will happen, when Frame Sync Error is occurred?

  • Hi,

    The Frame sync error may caused due to frame syncs that are occurring early even before the last transmit or receive completes.

    When a serial port is receiving or transmitting, it's bit count is set to a word length (for example SLEN = 32 bits). After each clock edge the bit count is decremented. After the word is received/transmitted the bit count reaches zero, and on next frame sync it is set to 32.

    When active transmission or reception is occurring, the bit count value is non-zero. When a frame sync with a bit count of non-zero is detected, a frame sync error occurs.

    We would suggest you to refer "Frame Sync Options" (Pg No:1052) "Premature Frame Sync Error Detection" (Pg No:1055) and "Error Detection (Status) Interrupt" (Pg No:1072) in ADSP-21569 HRM.

    Anand Selvaraj.

  • Dear Anand,

    Thank you for your reply.

    Could you answer me some more questions?

    (a) When Frame sync error has occurred, what happens in processor.
          My problem is 8 bits from MSB or 12bits from LSB are all zero data anytime when Frame sync error has occurred.

    (b) When Frame sync error is been cleared after this error has occurred? Only power off?

    (c) Is the countermeasure that enable MASK for this error bit effective about the problem written in (a)?

    Masa Hibino

  • Hi Masa Hibino,

    Apologies for the delay.

    FSERRSTAT bit under SPORT ERR register shows the status of the FS Error. Using the FS error mask bit in the same register an interrupt on FS error can be generated.

    When a half SPORT is receiving or transmitting, its bit count is set to a word length (for example, SPORT_CTL_A.SLEN = 31). After each serial clock edge, the half SPORT decrements the transfer's bit count. After the word is received or transmitted, the transfer's bit count reaches zero, and the half SPORT resets it (for example, to 32) on next frame sync. Normal SPORT data transfers always have a non-zero bit count value when active transmission or reception is occurring.
    FS error is generated when the half SPORT has detected a NEW frame sync when the bit count (bits remaining in the frame) is non-zero. Normal SPORT frame syncs occur after the bit count becomes zero.
    So, since a new FS is detected in between, the processor will leave the remaining data and it starts sampling from the again which will cause into complete data mismatch. It may result into causing the TX underflow/RX overflow as well.
    To clear the FS error, Clear the source of the interrupt by writing-1-to-clear the SPORT_ERR_A.FSERRSTAT, SPORT_ERR_A.DERRPSTAT, or SPORT_ERR_A.DERRSSTAT status bits. And a complete re-initialization of SPORT device (Configure SPORT, Configure DMA, Enable DMA, Enable SPORT) would be required again.