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ADAU1446 clock domain clarification

Am planning to use the ADAU1446 to receive digital audio in a variety of formats, possibly process it with Sigma Studio functions, then spit it out in different formats. At the basic level, I'm using it as a pass through format converter. All inputs and outputs are on the same 24.576MHz MCLK domain fed to the chip. Inputs and outputs will be 48KHz audio in either I2S, TDM8, or TDM16 formats.

Some things are not quite clear to me from the datasheet. For example:

  1. I think I can take in 8 channels of I2S and output 1 TDM16 channel. I think I will need to set the associated output clock pair as a master, and configure it for the TDM16. Does the output clock pair need to correspond to the same port number as the output serial data port that is emitting the TDM16? I assume yes but it is not explicitly stated.
  2. What about the opposite situation where I take in one TDM16 channel and spit out 8 serial channels of I2S. Can I slave them all to one clock output port set as a master in I2S mode? On p. 34 the data sheet says "a clock domain in master mode can only clock a single serial port". That would imply I can't, but surely it must be the case that I don't have to tie up 8 clock input ports for the sake of outputting 8 serial data streams in I2S mode. I plan to have a variety of other input clock sources and input serial streams in a variety of formats that can be selected for processing and or pass through.

Some clarification on these points would be greatly appreciated.