Hi Forum
I have an application that runs fine in the field.
However rarely the board resets, due to watchdog reset, but I have yet to see in in LAB.
As my program uses the L2 memory, for both program and data, I am wondering if it could be an error in the L2 memory that causes the reset. I have not disabed the ECC, for any part of the L2 memory.
If I read the manual it states:
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An ECC multi-bit error in an ECC-enabled bank. A non-modulo, 32-bit write to an ECC-enabled bank can
also potentially create a bus error response due to an ECC multi-bit error. This response is because the L2 system
memory implements a 32-bit ECC, and therefore a non-modulo, 32-bit write results in a read. This read
can create multi-bit errors even if the memory was initialized.
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Could this cause a reset? And would it help to disable the ECC for the data part?
Alternatively I also read from the manual:
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If data in L2 SRAM contains single-bit errors, the data is corrected on its way to the system buses. The corrected
value is not written back to the SRAM location. To prevent any risk of accumulation of single-bit errors over time
and to minimize likelihood of multi-bit errors, the L2 system memory provides a special memory refresh mechanism.
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Could this be the cause, that errors are build up? How likely is that, and should I enable SCRUB.. and how does it work?
