About SPI0 communication: when EMISO of SPI_CTL registers is disabled, does output terminal is set as "Hi-z"? (ADSP-21569)

Hello, 

Could you tell me below,

About SPI0 communication: when EMISO of SPI_CTL registers is disabled, does output terminal is set as "Hi-z"? 

(DSP device is ADSP-21569)


I would to avoid collision between multi slave SPI device MISO signals.

BR,

Masa Hibino

  • Hi Masa Hibino,

    The SPI_CTL.EMISO bit enables master-in-slave-out (MISO) mode. This SPI mode is applicable only when the SPI is a slave.
    When all the slaves are processors, then the requester can receive data from only one processor at a time. (The functionality is enabled by clearing the SPI_CTL.EMISO bit in the six other slave processors.) For more information on this please refer the SPI chapter in  ADSP-2156x hardware reference manual.
    You can download the manual from the below link,
    www.analog.com/.../adsp-2156x_hwr.pdf

    Regards,
    Anand Selvaraj.