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ADSP-BF51x L1 allocations

Tools: CCES 2.2.0, ADSP-BF518F EZBOARD
On the ADSP- B51x can an L1 data bank(ex. B) be allocated for instruction or can an instruction bank be allocated for data? Perhaps a modification to the LDF file?

If so, what are the ramifications?

Is there bus contention?

Can all(except scratch) of L1 be allocated to either code exclusively of data exclusively? This assumes there is an external allocation for the other one.

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  • Thanks,

    I was not sure since the datasheet says the following:

    "Blackfin processors support a modified Harvard architecture in

    combination with a hierarchical memory structure. Level 1 (L1)

    memories are those that typicallyoperate at the full processor

    speed with little or no latency. At the L1 level, the instruction

    memory holds instructions only. The two data memories hold

    data, and a dedicated scratchpad data memory stores stack and

    local variable information." pg4

    ADSP-BF512_514_514F16_516_518_518F16

    Additionally in the ref. the Chip Bus hierarchy diagrams show data buses between the L1 and Processor core and showing data and instruction separately in multiple figures. I understand figures can often require clarification.

    ADSP-BF51x Blackfin Processor Hardware Reference

    I was able to re-assign Data Bank B cache(FF904000 - FF907FFF) and place some lib_code there.

    Thanks,

    Nathaniel

Reply
  • Thanks,

    I was not sure since the datasheet says the following:

    "Blackfin processors support a modified Harvard architecture in

    combination with a hierarchical memory structure. Level 1 (L1)

    memories are those that typicallyoperate at the full processor

    speed with little or no latency. At the L1 level, the instruction

    memory holds instructions only. The two data memories hold

    data, and a dedicated scratchpad data memory stores stack and

    local variable information." pg4

    ADSP-BF512_514_514F16_516_518_518F16

    Additionally in the ref. the Chip Bus hierarchy diagrams show data buses between the L1 and Processor core and showing data and instruction separately in multiple figures. I understand figures can often require clarification.

    ADSP-BF51x Blackfin Processor Hardware Reference

    I was able to re-assign Data Bank B cache(FF904000 - FF907FFF) and place some lib_code there.

    Thanks,

    Nathaniel

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