ADSP-BF51x L1 allocations

Thanks,

I was not sure since the datasheet says the following:

"Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typicallyoperate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information." pg4

ADSP-BF512_514_514F16_516_518_518F16

Additionally in the ref. the Chip Bus hierarchy diagrams show data buses between the L1 and Processor core and showing data and instruction separately in multiple figures. I understand figures can often require clarification.

ADSP-BF51x Blackfin Processor Hardware Reference

I was able to re-assign Data Bank B cache(FF904000 - FF907FFF) and place some lib_code there.

Thanks,

Nathaniel

After more testing I received an access violation when I tried to access code from the 0xFF90 000 memory region aka Data Bank B.

It appears I am able to store code there, but the proc. still thinks the region is for data. This means that trying to access the code results in a fault unless there is way to tell the proc. that its code.

A non-recoverable error or exception has occurred.

  Description:   Illegal instruction fetch access (memory protection violation) (Exception with EXCAUSE=0x2B).

  General Type:  UnhandledException

  Specific Type: InstructionFetchViolation

  Error PC:      0xff900000

Thanks,

Hi,

Apologies for any confusion

Please note that Blackfin L1 data memory can't be used for instructions and L1 instruction memory can't be used for data.

Please let me know if you need further details

Best Regards,

Kader