ADSP-21569 SPORT DMA RX Transfer

Hello

I have a problem with the proper setting of the SPORT interface with receiving data via DMA.

Currently, I was able to start receiving data through the SPORT interface using DMA using one list descriptor and to create cyclic buffer.

I am currently receiving 8 x 32bit word every 250us. And every 8 words I get a callback from SPORT.

But it happens automatically. Is it possible to set the DMA so that it receives only 8 words and ends the transfer, and inside the RX callback I start a new transfer of the next 8 words and indicate a new memory location (new pointer for rx data) for this next 8 bytes?


I tried to start new transfer inside the callback but I get an error that SPORT is in use etc.

Thank you in advance for your help!


Below is my current code:

static void PrepareDescriptors (void)
{
            Dest_List[0].pStartAddr           = &DestDataBuf[0];
            /* DMA Config - only specify memory transfer size */
            Dest_List[0].XCount               = (DMA_BUF_SIZE/DMA_MSIZE_IN_BYTES);
            Dest_List[0].XModify              = DMA_MSIZE_IN_BYTES;
            Dest_List[0].Config               = ENUM_DMA_CFG_XCNT_INT;
            Dest_List[0].YCount               = 0;
            Dest_List[0].YModify              = 0;
            Dest_List[0].pNxtDscp			  = &Dest_List[0];
}

static void PrepareDataBuffers (void)
{
    /* Loop variable */
    uint32_t loopvar;

    /* Generate Source data, Clear destination buffer */
    for (loopvar = 0u; loopvar < DMA_BUF_SIZE; loopvar++)
    {
        DestDataBuf[loopvar]  = 0u;
    }
}

/* SPORT callback function */
static void SPORTCallbackRx(
    void        *pAppHandle,
    uint32_t     nEvent,
    void        *pArg
)
{
	ADI_SPORT_RESULT eResult;
    /* CASEOF (event type) */
    switch (nEvent)
    {
        /* CASE (buffer processed) */

        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        	SPORTCallbackCount +=1;
            break;
        default:
       	    break;
    }
}

void SPORT_Init(void)
{
	*pREG_PADS0_DAI0_IE = BITM_PADS_DAI0_IE_VALUE;
	*pREG_PADS0_DAI1_IE = BITM_PADS_DAI1_IE_VALUE;

    SRU2(DAI1_PB05_O,SPT4_ACLK_I); /*SPORT clk from ADC*/
    SRU2(LOW,DAI1_PBEN05_I);

    SRU2(DAI1_PB04_O,SPT4_AFS_I);  /*SPORT fs from ADC*/
    SRU2(LOW,DAI1_PBEN04_I);

    SRU2(DAI1_PB01_O,SPT4_AD0_I); /* SPORT data from ADC*/
    SRU2(LOW,DAI1_PBEN01_I);

	/* Open SPORT 4A */

	int eResult = adi_sport_Open(SPORT_DEVICE_4A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory4A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4ARx);
	if (eResult != ADI_SPORT_SUCCESS)
	{
		return FAILED;
	}

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 4A*/
	eResult = adi_sport_ConfigData(hSPORTDev4ARx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev4ARx,0,false,true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev4ARx,0,true,false,false,true,true,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev4ARx,0u,7u,0u,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev4ARx,0u,7u);
	CHECK_RESULT(eResult);

	/* Register SPORT0B Rx Callback */
	eResult = adi_sport_RegisterCallback(hSPORTDev4ARx,SPORTCallbackRx, NULL);
	if (eResult != ADI_SPORT_SUCCESS)
	{
		return FAILED;
	}

	/* Prepare data buffers */
	PrepareDataBuffers();


	/* Prepare descriptors for memory copy using List mode */
	PrepareDescriptors();

	/* Submit the buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4ARx,Dest_List,(1),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	if (eResult != ADI_SPORT_SUCCESS)
	{
		return FAILED;
	}

	/* Enable SPORT 4A*/
	eResult = adi_sport_Enable(hSPORTDev4ARx,true);
	if (eResult != ADI_SPORT_SUCCESS)
	{
		return FAILED;
	}

	
		return SUCCESS;
}




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[edited by: Franciscus at 9:35 PM (GMT -4) on 15 Jul 2021]