TDM change audio channels after breakpoint

Hi !

i observe troubles if i halt the processor via a breakpoint.

After that my 8channel audio input&output) change the order of received channels and my in/outs are not the same.

is there an option to resync this with the converters- i thought that hardware recognizes this by using FS-signals ???

i use a BF607 and a cirrus logic CS5368 ADC and a CS4385(A) DAC which generates the SPORT signals

kind regards christoph

  • 0
    •  Analog Employees 
    on Dec 10, 2020 11:43 AM 4 months ago

    Hi,

    Please note that the frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. The serial port frame sync ( SPT_AFS) signal is considered a Receive Frame Sync if the transfer direction is configured as receiver; while it is considered a Transmit Frame Sync when configured as transmitter. Frame sync is also a control signal, generally used to determine the start of new word or frame. Upon detecting this signal, serial port starts shifting in or out the new data bits serially based on the direction selected. The frame sync signal can be internally generated from its serial clock (SPT_ACLK) or externally provided, based on the SPORT_CTL_A.IFS bit setting.

    Please refer the SPORT chapter (PageNo:1555 / 2278) in the HRM of ADSP-BF607. You can find the HRM from below link,
    www.analog.com/.../blackfin_hwr_bf60x_rev0.5.pdf

    Regards,
    Anand Selvaraj.

  • we use ext.AFS from ADC to receive data via 8channel TDM. The Problem is, that after a breakpoint ch1 is not longer ch1 this is maybe ch3 or channel 7 ?? therefore i have no idea why. the order is always correct .

    our settings . we use a ADC: CS5368 and 8-TDM Channels 

    and a DAC also from cirrus: CS4385

    #define SPENPRI_0 1 // Enable Primary channel
    #define SPENSEC_0 0 // Enable Secondary channel
    // 0 - Disable, 1 - Enable
    #define CKRE_0 1 // clock rising edge
    // 0 - Driving edge : rising edge, sampling edge : falling edge
    // 1 - Driving edge : falling edge, sampling edge : rising edge
    #define FSR_0 1 // Frame Sync required
    // 0 - FS not required, 1 - FS required
    //auto set if in MC-mode
    #define DIFS_0 0 // 0 - Data dependent frame sync, 1 - Data independent frame sync
    // reserved in MC-mode
    #define LFS_0 0 // frame sync polarity select or channel first select
    // when OPMODE = 0 : 0 - Active high frame sync, 1 - Active low frame sync
    // when OPMODE = 1 : 0 - right-channel first, 1 - left channel first
    #define SLEN_0 31 // serial word length select.
    // SLEN = (serial word length) - 1
    #define DTYPE_0 1 // Data type select
    // 0 - Right-justified mode, zero-fill unused MSBs
    // 1 - Right-Justified mode, sign-extend unused MSBs
    #define LSBF_0 0 // serial bit endian select
    // 0 - MSB sent/receive first, 1 - LSB sent receive first
    #define PACK_0 0 // 16-bit to 32-bit packing enable select
    // 1 - Enable packing, 0 - Disable packing
    #define GCLKEN_0 0 // 1 - Enable Gated clock mode, 0 - Disable Gated clock feature
    // In Multichannel mode: Reserved
    #define FSED_0 0 // 1 - Edge-sensitive detection for FS, 0 - level-sensitive detection for FS
    #define TFIN_0 0 // 1 - Transmit Finish interrupt (TFI) enable, 0 - TFI disable

  • 0
    •  Analog Employees 
    on Dec 31, 2020 12:44 PM 3 months ago in reply to pfeifferc

    Hi,

    1. Do you mean to say that you are able to see all the data are getting transmitter properly if you run the code without any breakpoint in the code?
    2. Where you are actually put breakdown?
    3. Are you breakpoint in the ISR? But when you put breakpoint in the ISR and send only one data you are observing the data sent twice. Your code snippet seems correct and we don’t find any obvious mistakes. BTW, please note that it is not recommended to put break point in the ISR since the SPORT clock is free running once it is enabled and by putting break point you are restricting its control.
    4. Can you please confirm if there is any problem when communicating with ADC/DAC, if the SPORT code is free running (without any break point)?

    Regards,
    Anand Selvaraj.

  • hi ! code & application works fine for 8input channels and 8outputchannels. the misbehaviour only happens if i stop the emulator. after a re-run the channels are not longer correct received.  

    application gets ch1-8 from CS5368 in tdm mode - after stop and rerun the first channel is no longer the ch1

    the 1st received channel is for example. CH4|Ch5|CH6|Ch7|CH8|Ch1|CH2|Ch3  or any other random starting channel - but the order is always ascending   ..one further example could be CH7|Ch8|CH1|Ch2|CH3|Ch4|CH5|Ch6

    if i stop&re-run again the starting channel is again a random channel ?

    so - no idea if Cirrus is doing this but frameSync should help to avoid such problems in my opinion

    kind regards chris

  • 0
    •  Analog Employees 
    on Feb 19, 2021 8:29 AM 1 month ago in reply to pfeifferc

    Hi,

    We always recommend customers to avoid placing break point in the audio code. If you put a break point in the audio code it is actually causing delay (halting).

    Regards,
    Anand Selvaraj.