Question aboat BF592A TDM mode ,DSP can't receive any datas,please help to check the code correct or not

Hi:

     In my design , the Dsp receive datas by sport0 (8channel-TDM mode) from FPGA .the sampling clock (384KHZ) and frame clock (1.5K) are generate by FPGA (in total 256bit a frame),please see the picture  below:

      

  now my question is the sport0 in TDM mode can't receiv any data.

     I am also looking for some relevant example code.

    So any one can give me some suggestions on these problems?

    Many thanks!

---Visoaldsp++ Codes:----------------------------------------------------------------------------------------------------------------------------------------------

//--------------------------------------------------------------------------//
// Function: Init_Sport0 //
// //
// Description: Configure Sport0 for TDM mode, to transmit/receive data //
// to/from the FPGA. Configure Sport for external clocks and //
// frame syncs. //
//--------------------------------------------------------------------------//

void Init_Sport(void)
{
// TDM
*pSPORT0_RCR1 = RFSR ;
*pSPORT0_RCR2 = SLEN(31) ;
*pSPORT0_TCR1 = TFSR ;
*pSPORT0_TCR2 = SLEN(31) ;

*pSPORT0_MTCS0=0x000000ff;
*pSPORT0_MRCS0=0x000000ff;


*pSPORT0_MCMC1=0; // 8channel
*pSPORT0_MCMC2=MCMEN;

}

//--------------------------------------------------------------------------//
// Function: Init_DMA //
// //
// Description: Initialize DMA1 in autobuffer mode 
//--------------------------------------------------------------------------//

void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;

// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_AUTO;
// Start address of data buffer
*pDMA1_START_ADDR = (void *)iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = BUFFERSIZE;
// Inner loop address increment
*pDMA1_X_MODIFY = 4;

}

void Enable_DMA_Sport(void)
{
// enable DMAs

*pDMA1_CONFIG = (*pDMA1_CONFIG | DMAEN);

// enable Sport0 TX and RX

*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
}

void Init_Interrupts(void)
{
// Set Sport0 RX (DMA1) interrupt priority to 1 = IVG9
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xfffFff2f;
*pSIC_IAR2 = 0xffffffff;

// assign ISRs to interrupt vectors
// Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, Sport0_RX_ISR);

// enable Sport0 RX interrupt
*pSIC_IMASK = 1<<9;

ssync();
}

EX_INTERRUPT_HANDLER(Sport0_RX_ISR)
{
// confirm interrupt handling
*pDMA1_IRQ_STATUS = 0x0001;

}

void Ini_PLL(void)
{
// CLKIN=24.576mhz;CCLK=122.88mhz;SCLK=61.44mhz;Clk_sport=SCLK/2=30.72mhz;
ADI_SYSCTRL_VALUES frequency;
/* Set MSEL = 5-63 --> VCO = CLKIN*MSEL */
frequency.uwPllCtl = SET_MSEL(5) ;
/* Set SSEL = 1-15 --> SCLK = VCO/SSEL */
/* CCLK = VCO / 1 */
frequency.uwPllDiv = SET_SSEL(2) |CSEL_DIV1 ;
frequency.uwPllLockCnt = 0x0200;
bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT, &frequency, NULL);

*pVR_CTL|=EXTCLK_OE;
}


int main( void )
{

*pPORTG_FER=0XFF;
Ini_PLL();
Init_Sport();
Init_DMA();
Init_Interrupts();
Enable_DMA_Sport();
while(1)
{

}

}

  • 0
    •  Analog Employees 
    on Feb 21, 2020 2:59 PM

    Hi,

    From the share code snippet it noticed that you have configured the corresponding RFSR and TFSR in SPORT_RCR1 and SPORT_TCR1 register which should be ignored in multichannel mode configuration.
    I would suggest you to refer the BF59x hardware reference manual (Table 14-3), Page.No 545 which shows the dependencies of bits in the SPORT configuration register when the SPORT is in multichannel mode.
    You can also look on Multichannel Operation chapter for more information on it. The HRM can be find from the below link,
    www.analog.com/.../ADSP-BF59x_hwr_rev1.2.pdf

    Regards,
    Anand Selvaraj.