CPLB miss

Hi, 

Regarding to an exception fault "CPLB miss without replacement", the RETX is "11A01B6A". 

Following this guide: https://ez.analog.com/dsp/blackfin-processors/f/q-a/59511/cplb-miss-exception/202507#202507 , I need to add a CPLB entry for the region of memory that covers this faulting address. What the CPLB entry can be?

Top Replies

  • 0
    •  Analog Employees 
    on Oct 15, 2019 2:19 PM over 1 year ago

    That's an address in L1 instruction SRAM and should be covered by the default CPLB registers that are initialized by the following code in the startup:

    #if __ADSPLPBLACKFIN__>=0x220
    // Initialize the default CPLB registers for L1 memory.
    // System memory is controlled by individual CPLB entries.

    // Load the data value into R0.
    R0 = BITM_L1DM_DCPLB_DFLT_L1UREAD | BITM_L1DM_DCPLB_DFLT_L1UWRITE | BITM_L1DM_DCPLB_DFLT_L1SWRITE | BITM_L1DM_DCPLB_DFLT_L1EOM;

    // Load the instruction value into R1.
    R1 = BITM_L1IM_ICPLB_DFLT_L1UREAD | BITM_L1IM_ICPLB_DFLT_L1EOM;

    // Write the values to the default CPLB registers.
    [REG_L1DM_DCPLB_DFLT] = R0;
    [REG_L1IM_ICPLB_DFLT] = R1;
    CSYNC;
    #endif /* __ADSPLPBLACKFIN__>=0x220 */

    Are you using a custom startup that might be missing this code perhaps?

    If somehow you are attempting to access instruction SRAM as data, then this CPLB miss is the error you would get and it indicates that some kind of bad access is being attempted, perhaps due to something like dereferencing an uninitialized pointer maybe. The address in RETX should be the location of or just before such a problem access and where to look to debug the problem.

    Regards,
    Stuart.


  • Mine looks like:

    // Initialize the default CPLB registers for L1 memory.
    // System memory is controlled by individual CPLB entries.

    // Load the data value into R0.
    R0 = BITM_L1DM_DCPLB_DFLT_L1UREAD | BITM_L1DM_DCPLB_DFLT_L1UWRITE | BITM_L1DM_DCPLB_DFLT_L1SWRITE | BITM_L1DM_DCPLB_DFLT_L1EOM;

    // Load the instruction value into R1.
    R1 = BITM_L1IM_ICPLB_DFLT_L1UREAD | BITM_L1IM_ICPLB_DFLT_L1EOM;

    // Write the values to the default CPLB registers.
    [REG_L1DM_DCPLB_DFLT] = R0;
    [REG_L1IM_ICPLB_DFLT] = R1;
    CSYNC;

    // initialize the CPLBs if they're needed. This was not possible
    // before we set up the stacks.

    I miss "#if __ADSPLPBLACKFIN__>=0x220"

  • The code that the CPLB miss is happening is here:

    #define ProgAdd              0xE8000

    unsigned int *tmp_pointer = 0;

    int temp_data;

    for(n_cnt=0;n_cnt<8;n_cnt++)

                   {

                       tmp_pointer = (unsigned int *) (((unsigned long)ProgAdd + 0x100 + i_cnt + n_cnt));

                       temp_data = *tmp_pointer;           // CPLB miss without replacement

                       CANTXData[n_cnt] = temp_data;

                   }

  • +1
    •  Analog Employees 
    on Oct 15, 2019 3:06 PM over 1 year ago in reply to SVA

    According to the memory map address 0xE8000 is reserved, ref the data sheet. If you are porting code from an older Blackfin part this would have been an address in SDRAM so I suspect that maybe you need to update the addresses being used here?

    Regards,
    Stuart.

    Edit1 - link fixed.