SC 58x DAI clearing latch register

Hi,

Hi I am trying to make a couple of DAI for the SC-589 work as falling edge interrupts. 

I have initialized the pin as follows

 SRU(LOW, DAI0_PBEN11_I);

SRU(DAI0_PB11_O, DAI0_INT_7_I)
*pREG_DAI0_IMSK_FE = 1U << 29;    // bit 29 is INT 7

adi_int_InstallHandler(INTR_DAI0_IRQL, (ADI_INT_HANDLER_PTR)ISR_HANDLER ,0 , true);

and  my ISR is 

void TACHOMETER_ISR_HANDLER(int iid, void *handlerArg)
{
if((*pREG_DAI0_IRPTL_L & 0x20000000)== 0x20000000 )
{
found_edge++;
*pREG_DAI0_IRPTL_L = 0x20000000; // W1C
}

}

The *pREG_DAI0_IRPTL_L = 0x20000000; // W1C does not compile.  The HRM says that to perform a W1C

operation to clear the latch.

Digging into further I searched that it is defined under ADSP_SC589_cdef

#define pREG_DAI0_IRPTL_L                ((__I __C  uint32_t  *) REG_DAI0_IRPTL_L)                /*  Low Priority Interrupt Latch Register */

If I search above this file, the attribute ___I is commented to be read only.

Is this the reason, the compiler complains? 

Please advise how to perform the W1C operation for this purpose.  

Thank you in advance for your response. 

Emilson 

  • 0
    •  Analog Employees 
    on Sep 30, 2019 11:09 AM over 1 year ago

    Hi,

    Form the ADSP_SC589_cdef.h "Low Priority Interrupt Latch"  Register is defined as constant memory address. So we cannot able to assign a value to the register.

    As per SC589 Hrm Page no: 2640, "Low Priority Interrupt Latch"  Register is read only. We can read the status bit of the register. It is write protected.

    The ADSP_SC589_cdef.h file is defined as per HRM.

    You have to enable "pREG_PADS0_DAI0_IE,pREG_PADS1_DAI0_IE"  register in order to enable DAI inputs.

    We have also tested your code it is entered into ISR.

    Please find the below link:

    ez.analog.com/.../adsp-sc58x-2158x-dai-example-code

    Regards,
    Anand Selvaraj.

  • 0
    •  Analog Employees 
    on Sep 30, 2019 1:41 PM over 1 year ago

    I've emailed the hardware designer responsible for DAI to get details as it does seem that either the HRM text or the pREG_DAI0_IRPTL_L macro may need a correction. I'll post back when I hear anything.

    Regards,
    Stuart.

  • Anand,

    Thank you for your response.  The challenge that I am facing is how to restart the interrupt mechanism. The HRM mentions that I have to do a W1c operation to clear it. So my impression is the code should be

    1. setup pin and isr vector and code.

    2. interrupt happens -> process

    3. W1c to a specific register

    4. Idle or do other stuff till #2 happens again. 

    I am more wondering how to do the step 3 so I can retrigger again.

    Let me know if you have further insights. 

    Thanks,  

    EE

  • Stuart, 

    Thank you for your response. I look forward if there is a correction that can be done. The HRM does mention a W1C

    somewhere to re-enable the interrupt vector. So it is more of a clarification maybe of what register to W1C to restart the process or if there is a different recommended procedure .Either way, thank you for your help. 

    Emislon

  • 0
    •  Analog Employees 
    on Oct 11, 2019 11:04 AM over 1 year ago in reply to emenrique

    Hi,

    The design engineer has updated the text for future revisions of the manuals to the following

      “The DAI_IRPTL_L register holds the low priority latched interrupt status for interrupt requests that have been unmasked (enabled) by the DAI_IMSK_FE, DAI_IMSK_RE or DAI_IMSK_PRI registers. If a bit in DAI_IRPTL_L is already set and the corresponding interrupt is masked in DAI_IMSK_FE, DAI_IMSK_RE or DAI_IMSK_PRI registers, the latch holds its old value, leaving the interrupt asserted until its mask registers (DAI_IMSK_FE, DAI_IMSK_RE or DAI_IMSK_PRI) are reset by software with a W1C operation”

    Regards,
    Stuart.