How to boot dual-core application from non-default location in SPI Flash?

Hi, All ADI experts

My question: how to boot dual-core application from non-default location in SPI Flash?

Environment: BF607 , CCES 2.8.3 , emulator ICE1000, the flash is wired to SPI0.

  1. I wrote dual-core application: bf607_test_Core0 and bf607_test_Core1.The two application transfer data to each other by shared memory and the shared memory is a buffer allocated from a memory pool block at the section (0xc8080420-0xc8082c1f) which the two Cores can access both.
  2. My CCES setup for dual core-application (in Post-build steps field) to produce the ldr file of dual core.
  3. In property of core1 project, add a loader switch -NoFinalTag ../../bf607_test_Core1/Release/bf607_test_Core1.dxe.
  4. If I run this application via Emulator: it works OK (both cores OK)
  5. If I programmed ldr file of dual-core application into default location in SPI Flash (0x00000000) and press RESET :  it works OK (both cores OK)
  6. I programmed ldr file of dual-core application into any different location ( i.e. 0x00014000 ) and I wrote a dual-core second_stage_loader(ssl): bf607_SSL_Core0 and bf607_SSL_Core1 similarly. The two application of ssl also transfer data to each other by shared memory. I want to use ssl to boot application. Each core use rom_Boot () function to boot each application, core0 calls rom_Boot(0x00014000, 0, 0, 0, 0x20210002, 0) to boot application of core0 and core1 also calls rom_Boot(0x00014000, 0, 0, 0, 0x20210002, 0) to boot application of core1. I programmed ldr file of ssl into default location in Flash (0x00000000) and press RESET : the ssl works OK (both cores OK). After I let the dual-core ssl to boot the dual-core application, the result is the following two situations:
  • If core0 boots first and core1 boots after, core0 boots successfully and works normal, but rom_Boot of core1 not been executed.
  • If core1 boots first and core0 boots after, core1 throws an exception:

//////////////////////////////////////////////////////////////////////////////////////////////////////

A non-recoverable error or exception has occurred.

  Description:   An instruction CPLB miss has occurred without a corresponding CPLB entry.

  General Type:  RunTimeError

  Specific Type: ICPLBMissWithoutReplacement

  Error PC:      0xffa00000

//////////////////////////////////////////////////////////////////////////////////////////////////////

after, core0 boots failure.

I checked several times and got the same result:

The L1 Instruction SRAM in core0 seems have been overwritten after core1 boot.

So I am surprise why the same file of dual-core works properly from default location but doesn't work from any other?

Why does only core0 run if the ssl is used to load the dual-core application?

Is the method of ssl booting the dual-core application not correct?

Where is the problem?  Could anybody help me, please?

Thank you in advance

Williams