(ADSP-21571)About SPI(non-DMA) TFIFO


I use SPI0 (slave) with non-DMA.

The settings are as follows.

- SPI0_CTL.SIZE = 2(32bit word)

- SPI0_CTL.SIZE = 1(Enable)

- SPI0_TXCTL.TDU = 1(Send zeros when SPI_TFIFO is empty)

I want to output data in synchronization with the clock from the master after writing to the TFIFO register (SPI0_TFIFO).

However, the data is actually output in the later word.

I have a question.


TFIFO is described in the Hardware Reference Manual that there are two 32-bit word sizes.

I understand that this has a total size of 64 bits.

If TXCTL.TDU = 1, does Zero perform 64bit write to TFIFO regardless of CTL.SIZE?

(If SIZE is set to 32 bits, will 0 data be output twice?)


If the answer to question 1 is YES, is there a way to clear only 32 bits?

Best regards


  • +1
    •  Analog Employees 
    on Mar 25, 2019 2:42 PM


    As the size of the SPI transfer has configured to 32 bit, SPI would only make a 32 bit transfers until the SPI_SS desserts.

    Please find the HRM information in section " Slave Operation in Non-DMA Modes ", "The slave device continues to receive or transmit with each new falling edge transition on SPI_SS or active SPI_CLK edge. If the transmit buffer remains empty or the receive buffer remains full, the device operates according to the states of the SPI_TXCTL.TDU and SPI_RXCTL.RDO bits"

    Lalitha S