There is a Flash programming problem for BF703.
I referred to the EE-372 document to develop LED Blink example on a self target board.
The program worked under debug mode.
The bf707_w25q32bv_dpia.dxe had been modified for flash W25Q128JVPIQ and The CLKIN had been modified in int_BF707.dxe.
CCES invoked CLDP.exe to program flash and it was done. Power cycled the board but boot failed from flash.
I can ascertain that the board is workable because the other process worked normally.
There must be some issues. Please help me to fix it.
Hi ALII-D, First to note that as of revision 1.0 and beyond, the Boot kernel enables the instruction cache during booting, and leaves it enabled; applications which use the SRAM/ICache space as SRAM cannot be booted directly into that space; they first need to ensure that an initcode runs which disables the instruction cache. This is in case if you code example is big and accessing SRAM/ICache space as well.
BTW, in order to identify if the you are seeing boot failure or functional failure in the custom board, we have below suggestion and it would be helpful if you can revert with the answers. 1) I understand that you are just doing an LED blink code. Can you please try keeping the silicon version as 'ANY' in the project option and see if the failure is still happening?
In future if you are using any utility ROM contents in the application code, be aware of the below points as well. The ADSP-BF70x parts have two components to their ROM – the Boot ROM and the Utility ROM. The Boot ROM handles the booting process, and the Utility ROM contains copies of some system services, device drivers, common runtime library functions, and a configuration of the uC/OS RTOS. It is not required for booting. The Utility ROM contents differ from silicon revision to silicon revision, so your application may malfunction. If you plan to run your application on more than one silicon revision of the processor, you cannot use the Utility ROM, so –no-utility-rom is needed. If you build your application for silicon revision any, then it needs to run on more than one silicon revision, so the tools automatically apply –no-utility-rom in this case. 2) Please ensure that the /TRST signal of the JTAG ICE is connected to board ground. Do not leave this signal floating. Letting this signal float may cause boot failures or other memory access failures. 3) Can you probe clock and reset signals to the processor and confirm that the timing requirements are correctly followed as mentioned in the 'Clock and Reset Timing' specification table in the ADSP-BF707 datasheet. Please refer to the Figure.10 (Page 60 of 11) from the datasheet for more information. 4) Can you also debug the code as per the FAQ: How to debug a target board which boots from Flash using CrossCore Embedded Studio, the link is given below. https://ez.analog.com/dsp/software-and-development-tools/visualdsp/w/documents/9552/faq-how-to-debug-a-target-board-which-boots-from-flash 5) Can you double confirm the SYS_BMODE1-0 pins are correctly configured for SPI master booting? Regards, Jithul