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PCG trigger mode reset

Category: Hardware
Product Number: ADSP-2156x
Software Version: CCES

I am trying to construct I2S clock and frame sync  by using the PGC in trigger-mode, hoping to synchronize to an external periodic event. 

The very first cycle, the signals are generated as advertized -- 2.5 - 3.5 cycles (of internal sys clk) after the event, both FS and clock transition. 

However, thereafter, they just free run while ignoring the trigger.

Is there a way to make it always re-sync to the trigger, any time the event occurs?

I don't see this addressed in the documentation.

  • Hi,

    We suggest to refer the External Event Trigger Delay (Page no:1138/2331). The link for the ADSP-21569 Hardware Reference Manual is given below.

    Can you please provide your comments on the below points.
    1. For our understanding, Are you using a Internal or external Clock?
    2.Can you please give the details in probe image, which one is Clock Input , External Trigger Input and Frame Sync(Output)?

    Anand Selvaraj.