The ADC can operate with a max sample rate of 2Msps when supplied with VDD=5V.
The processor pin descriptions in the data sheet do not show a separate supply for the ADC and the processor's VDDext is specified at 3.3V. So my question is, is there a separate Vdd for the ADC and when this is connected to 5V is there any issue in interfacing to the 3.3V io ring of the processor?
All ADC signals are brought out to BF506F package pins and appear in the ADC Signal Descriptions table of the data sheet.
There are separate Vdd signals for the ADC:
- The ADC's analog supply, which powers all analog circuitry, is at AVdd.
- The ADC's digital supply, which powers all digital circuitry, is at DVdd.
- The ADC's logic power supply, which determines the voltage that the interface operates at, is at Vdrive.
In order to achieve the maximum sampling rate of 2MSPS while interfacing the ADC's I/O signals to the processor's I/O signals, which operate at 3.3V:
- AVdd and DVdd should be supplied by 5V (AVdd and DVdd should not be more than 0.3V apart, even on a transient basis).
- Vdrive should be supplied by 3.3V (Vdrive can be supplied by voltages in the range 2.7V - 5.25V, but should never exceed either AVdd or DVdd by more than 0.3V))