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Blackfin Processors
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Blackfin Processors
Documents How to create a bootable LDR file of Lockbox Security example?
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Blackfin Processors requires membership for participation - click to join
  • +Documents
  • ADSP-BF537 - Memory test
  • Anomaly (05-00-0495) affecting ADSP-BF50x revision 0.0
  • Blackfin GPIO Open-Drain Functionality
  • BLACKFIN PROCESSORS
  • Booting an application from internal flash in BF50xF processors
  • Controlling multiple ADCs with the ACM
  • DAS U-BOOT FOR BLACKFIN SUPPORT COMMUNITY
  • FAQ: ADSP-BF527 Multi dxe boot
  • FAQ: ADSP-BF592 SPI loopback
  • FAQ: BF51x OTP memory read and write on GP space using CCES
  • FAQ: BF592 SPORT Example code
  • FAQ: Does ADI has BF702 USB Device Examples without using uCOS?
  • FAQ: Example code for ADSP-BF548 UART Full duplex communication across two Ez-kits
  • FAQ: Get total code and data size from Blackfin linker
  • FAQ: How do I reconcile Blackfin SPI serial clock phase control (CPHA) settings with potentially conflicting hardware/software slave select modes, when both these attributes are managed by the same control bit?
  • FAQ: How do I restore the original SDP image to flash on my SDP board?
  • FAQ: How do you generate safe and strong keys in Lockbox?
  • FAQ: How to access global variables for multi cores
  • FAQ: I have a Blackfin based USB application for which I've enabled (unmasked) the Connect and Disconnect interrupts, however, when I plug and unplug the USB cable no interrupt is generated. Why is this?
  • FAQ: I'm interested in the Blackfin processor family but don’t know where to start?
  • FAQ: Lockbox on EZ-Kits
  • FAQ: One .ldf file for release and debug
  • FAQ: USB:: Disabling Double Buffering
  • FAQ: Using the Blackfin SDP-B as a BF527 Evaluation Platform
  • FAQ: VisualDSP++ Workaround for SPI Boot Anomaly 05-00-0490
  • FAQ: What is Lockbox?
  • FAQ:  Blackfin and IEEE 1588
  • FAQ:  Can the ADC in BF506F be powered at 5V while interfacing to 3.3V signals?
  • FAQ:  CLI and "Target option Mask interrupts during step"
  • FAQ:  Connecting I2S via SPORT
  • FAQ:  External vs. Internal Voltage Regulator
  • FAQ:  How is the internal flash of BF50xF processors programmed?
  • FAQ:  How to boot the BF537?
  • FAQ:  Slow down start-up of internal regulator of BF525C processor
  • FAQ:  Unused PPI port pins
  • FAQ:  USB hub use with BF54x/BF52x USB controller
  • Floating point to integer conversion error
  • How Can I Boot A Blackfin Processor from an Atmel DataFlash SPI Memory Device?
  • How to create a bootable LDR file of Lockbox Security example?
  • How to Transfer Data Across Two EZ-KITs via USB
  • image processing demo for BF527
  • Impact of New On-Chip Flash for BF51xF Designs
  • Is There A Recommended DHCP Server Test for Blackfin and LwIP?
  • SDRAM Discontinuation
  • suggest me for correct datasheet
  • Trouble Transferring16-Bit Data on Blackfin SPORT
  • USB VBUS PROTECTION
  • What training is available for ADI DSPs
  • Where Can I Find the Blackfin assembly code for Cordic Algorithm?

How to create a bootable LDR file of Lockbox Security example?

The Lockbox overlay project in the Visual DSP++ installation (...\VisualDSP 5.0\Blackfin\Examples\ADSP-BF527 EZ-KIT Lite\lockbox) requires some

additional process in order to create a proper bootable LDR image. Without this, booting the original code fails with authentication failure.

Apparently, the post build command for digital signing of the secure sections in application dxe was called after Loader file (LDR) generation, thus failing any subsequent authentication. In order to overcome this, you could have the Project Options set for Executable file, and then generate LDR file by explicitly invoking the elfloader with another post build command.

Note that you will need to extract the exact elfloader.exe options for this new post build command. For that, you should first set the Project Options for Loader file, turn on verbose through “Settings: Preferences: Project: Verbose build output”, and then copy the entire relevant line from the VDSP verbose output after a project build (you can see the verbose being printed on the VDSP console, when the project is being built with the VDSP toolchain).

Once you capture the options you can copy the same to your post build command - which is generally a one-time procedure. Example build command tested for 0.2 Si with VDSP Update 8 is given below:

Serial boot:

"C:\Program Files\Analog Devices\VisualDSP 5.0\elfloader.exe" .\temp\Debug\pre-collaudo_92530.dxe -b SPI -f HEX -Width 8 -init "C:\Program Files\Analog Devices\VisualDSP 5.0\Blackfin\ldr\ezkitBF527_initcode_ROM-V02.dxe" -o .\temp\Debug\pre-collaudo_92530.ldr -No2Kernel -si-revision any -proc ADSP-BF527

Parallel boot:

"C:\Program Files\Analog Devices\VisualDSP 5.0\elfloader.exe" .\temp\Debug\pre-collaudo_92530.dxe -b Flash -f HEX -Width 16 -init "C:\Program Files\Analog Devices\VisualDSP 5.0\Blackfin\ldr\ezkitBF527_initcode_ROM-V02.dxe" -o .\temp\Debug\pre-collaudo_92530.ldr -No2Kernel -si-revision any -proc ADSP-BF527

The same issue and workaround should be applicable for BF548 Lockbox example as well.

...\VisualDSP 5.0\Blackfin\Examples\ADSP-BF548 EZ-KIT Lite\lockbox

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