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Blackfin Processors
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Blackfin Processors
Documents How Can I Boot A Blackfin Processor from an Atmel DataFlash SPI Memory Device?
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Blackfin Processors requires membership for participation - click to join
  • +Documents
  • ADSP-BF537 - Memory test
  • Anomaly (05-00-0495) affecting ADSP-BF50x revision 0.0
  • Blackfin GPIO Open-Drain Functionality
  • BLACKFIN PROCESSORS
  • Booting an application from internal flash in BF50xF processors
  • Controlling multiple ADCs with the ACM
  • DAS U-BOOT FOR BLACKFIN SUPPORT COMMUNITY
  • FAQ: ADSP-BF527 Multi dxe boot
  • FAQ: ADSP-BF592 SPI loopback
  • FAQ: BF51x OTP memory read and write on GP space using CCES
  • FAQ: BF592 SPORT Example code
  • FAQ: Does ADI has BF702 USB Device Examples without using uCOS?
  • FAQ: Example code for ADSP-BF548 UART Full duplex communication across two Ez-kits
  • FAQ: Get total code and data size from Blackfin linker
  • FAQ: How do I reconcile Blackfin SPI serial clock phase control (CPHA) settings with potentially conflicting hardware/software slave select modes, when both these attributes are managed by the same control bit?
  • FAQ: How do I restore the original SDP image to flash on my SDP board?
  • FAQ: How do you generate safe and strong keys in Lockbox?
  • FAQ: How to access global variables for multi cores
  • FAQ: I have a Blackfin based USB application for which I've enabled (unmasked) the Connect and Disconnect interrupts, however, when I plug and unplug the USB cable no interrupt is generated. Why is this?
  • FAQ: I'm interested in the Blackfin processor family but don’t know where to start?
  • FAQ: Lockbox on EZ-Kits
  • FAQ: One .ldf file for release and debug
  • FAQ: USB:: Disabling Double Buffering
  • FAQ: Using the Blackfin SDP-B as a BF527 Evaluation Platform
  • FAQ: VisualDSP++ Workaround for SPI Boot Anomaly 05-00-0490
  • FAQ: What is Lockbox?
  • FAQ:  Blackfin and IEEE 1588
  • FAQ:  Can the ADC in BF506F be powered at 5V while interfacing to 3.3V signals?
  • FAQ:  CLI and "Target option Mask interrupts during step"
  • FAQ:  Connecting I2S via SPORT
  • FAQ:  External vs. Internal Voltage Regulator
  • FAQ:  How is the internal flash of BF50xF processors programmed?
  • FAQ:  How to boot the BF537?
  • FAQ:  Slow down start-up of internal regulator of BF525C processor
  • FAQ:  Unused PPI port pins
  • FAQ:  USB hub use with BF54x/BF52x USB controller
  • Floating point to integer conversion error
  • How Can I Boot A Blackfin Processor from an Atmel DataFlash SPI Memory Device?
  • How to create a bootable LDR file of Lockbox Security example?
  • How to Transfer Data Across Two EZ-KITs via USB
  • image processing demo for BF527
  • Impact of New On-Chip Flash for BF51xF Designs
  • Is There A Recommended DHCP Server Test for Blackfin and LwIP?
  • SDRAM Discontinuation
  • suggest me for correct datasheet
  • Trouble Transferring16-Bit Data on Blackfin SPORT
  • USB VBUS PROTECTION
  • What training is available for ADI DSPs
  • Where Can I Find the Blackfin assembly code for Cordic Algorithm?

How Can I Boot A Blackfin Processor from an Atmel DataFlash SPI Memory Device?

Atmel DataFlash memory devices require a slightly different command sequence to load data for booting. The boot kernel of some Blackfin processors (ADSP-BF531/BF532/BF533/BF538/BF539) has a special built-in mode to accommodate these needs. If the SPI master mode is selected, the boot kernel performs a device detection sequence by issuing a 0x03 command followed by a zero address to the SPI bus. The SPI then counts cycles until data other than 0xFF (due to the pull-up on MISO) is returned. If no data is returned after three address bytes are issued, the boot kernel assumes that an Atmel DataFlash device might be out there and activates the required reading mode.

The above method works fine with the AT45DBxxxB parts from Atmel. However, with Atmel’s later AT45DBxxxD family of parts, the behavior changes slightly. The AT45DBxxxD DataFlash devices respond to the 0x03 command. However, they do not meet standard SPI addressing modes because of the DataFlash’s default page size of 264, 528, or 1056 bytes (depending on the device density). As a result, the boot kernel will properly read the first page of the memory and fail in reading all other pages.

All newer AT45DBxxxD DataFlash devices support the "power-of-2" (Binary) addressing mode. In this mode, the page size is limited to standard sizes (256, 512, ... bytes). The part responds to 0x03 (and also to 0x0B) commands and, therefore, behaves like a standard 3-byte addressable SPI memory.

DataFlash devices in power-of-2 mode can boot all existing Blackfin processors.

A One-Time-Programmable Bit has to be programmed by a special command to place an off-the-shelf DataFlash device into this power-of-2 (binary) page mode. Recent DataFlash devices no longer require a subsequent power cycle in order for the power-of-2 mode to be activated once the bit has been programmed. Please consult the respective device datasheets for further details. Additionally, Atmel is offers factory-configured power-of-2 page size devices with trailing 'SL954 or SL955' part number signatures where the OTP bit is factory-programmed.

An applications article http://www.atmel.com is available for reference on ordering factory-configured power-of-2 page size devices.

More recent Blackfin boot kernels (those embedded on ADSP-BF51x, ADSP-BF50x, ADSP-BF592, ADSP-BF52x and ADSP-BF54x processors) no longer have special support for DataFlash memories. Instead, it is assumed that all customers are using the 'D' Family of devices and have the option to let the part operate in power-of-2 mode.

DataFlashRegistered is a registered Trademark of Atmel Corporation.

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