Asynchronous Memory-bank controller unexcepted behavior

I have a custom board interfacing the BF527 to an FPGA through EBIU. I am using only 8 lines on the databus :D7 to D0,(D15 to D8 are unconnected). I have written the interface for Asynchronous Memory-bank Controller in VHDL. In order to test my VHDL behavior I am trying to read a total of 0x2fe bytes at blackfin sequentially in the order 0xff,0xfe,0xfd...0x00,0xff,0xfe...,0x00,0xff,0xfe,...,0x01, and halting at first error in reading. Read is done at fixed(even) address 0x20000000. The AMC is configured at maximum number clock cycles for SETUP, READ_ACCESS and HOLD (I can share the blackfin driver if needed). In my VHDL code every time I observe the AMS & AOE asserted I decrement a counter and output its value on the databus throughout the duration ARE is asserted.

I am observing an error in reading at exactly same location every time (i.e. exactly in reading 0x7f during the last chunk between 0xff,0xfe,...,0x01). At this instance blackfin is issuing a (dummy) read cycle by asserting the AMS,AOE and ARE, however no data is read in this cycle. Data read by blackfin is : 0x81,0x80,0x7e (0x7f is skipped because is transferred by FPGA during the dummy read cycle, and hence read is terminated)

I have attached a screenshot of a chipscope waveform depicting the same.

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(tx_done is my internal signal to know de-assertion of ARE)