Post Go back to editing

SPI clock not configurable

Thread Summary

The user encountered issues with SPI configuration on the ADSP-BF702 processor, specifically with the SCK line showing no activity. The solution involved enabling the pin multiplexing for SPI1 pins in the system.svc Pin Multiplexing tab. The SPI clock frequency is calculated as SCLK / (Clock + 1), and a value of 99u results in a 1 MHz frequency if SCLK0 is 100 MHz. The user also resolved an issue with configuring core and system clocks, reducing the sys_clkout from 20 MHz to a desired lower frequency.
AI Generated Content
Category: Hardware
Product Number: ADSP-bf702

Dear Team,

We are currently working on configuring the SPI lines for the ADSP-BF702 processor using the example code provided for the ADSP-BF706 EZ-KIT. While we are able to successfully configure the BF706 using the sample project, the migrated project for the BF702 does not result in the expected SPI configuration. Specifically, we observe that the SCK line does not show any activity, despite verifying the connectivity thoroughly.

Could you please assist in identifying any potential issues or configuration steps that may have been overlooked during the migration? For your reference, I have attached the migrated project in a ZIP file.

Additionally, we noticed that when setting the SPI clock value to 99u, the resulting frequency on the SPI lines is 1 MHz. Could you clarify if any internal calculation or conversion is being applied during this process?

SPI_ADSP-BF702.zip

Regards,
ES

  • Hi ES,

    We have analysed your project and noticed that the pin multiplexing for SPI1 pins has not been enabled. Please follow the steps below to configure the GPIO pins for SPI.

    1.Open the project in CCES
    2.Go to system.svc > Pin Multiplexing tab > Enable the SPI pins as in the attached image.

    3.Click Save and Run the project.

    After enabling the pin mux, please observe the SPI1 lines and let us know the results.

    Regarding SPI clock, the SPI clock frequency is determined by the formula: SCLK / (Clock + 1). In this case, the value 99u passed to the adi_spi_SetClock() API represents the "Clock" parameter, and the SPI clock is derived from the SCLK0.

    For example, if the SCLK0 is 100 MHz, the SPI clock would be calculated as 100 MHz / (99 + 1) = 1 MHz.

    Regards,
    Nandini C

  • Hi Nandini

    Thank you for the reply, but I have another quick doubt to ask, I'm trying to config core cclk and sclk but after configuration when I probe and check in the scope no change is happening by default my sys_clkout is set to 20MHZ, but I want to reduce it so I configured follwing.

    #define CLKIN (2000000)
    #define CCLK (20000000)
    #define SCLK (CCLK/5)

    int power_init(int state)
    {
    if (adi_pwr_Init(0, CLKIN) != ADI_PWR_SUCCESS)
    {
    perror("Failed to initialize power service \n");
    return 0; // failure
    };

    if (adi_pwr_SetFreq(0, CCLK, SCLK) != 0)
    {
    perror("Failed to config Core or Sysclk failed");
    return 0;
    }
    return 1;
    }

    is ther anything cfg is wrong?

    regards,
    ES

  • Hi Nandini,

    Thank you for your support, I have found where I have made the mistake now its fine, you can close this thread.

    Regards,
    ES