CPLB miss exception

My program works for a while and then halts at IDLE in the assembler routine "_cplb_miss_without_replacement". How do I solve this?

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    •  Analog Employees 
    on Apr 6, 2009 1:06 PM

    This exception occurs because you do not have a valid CPLB entry for the region of memory that you are accessing. When the Blackfin processor issues a memory operation for which no valid CPLB (cacheability protection lookaside buffer) descriptor exists in an MMR pair, an exception occurs. This exception places the processor into Supervisor mode and vectors to the MMU exception handler.

    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.

     

     

     

     

     

    The Blackfin Programming Refernce Manual has more details on this error. The Table titled "Events That Cause Exceptions" in the chapter "Program Sequencer" gives details on the different exceptions. The type of exception caused, and the reason why it is caused can be identified by viewing the EXCAUSE field in the SEQSTAT register (Register -> Core -> Status -> Sequencer Status).

     

     

     

    From the table of EXCAUSE values, you can identify if you have got an instruction CPLB miss or a data CPLB miss. If it is an instruction CPLB miss, you can find the instruction that caused it to happen by looking at the RETX register. (Register -> Core -> Sequencer -> RETX). Also, the faulting address can be found from the I/DCPLB_STATUS registers. You can now add a CPLB entry for the region of memory that covers this faulting address.


    If you have used up all 16 CPLB entries, then you will have to dynamically manage the CPLBs to service this exception, by having a CPLB replacement policy in place. The exception handler uses the faulting address to index into the Page Descriptor Table structure to find the correct CPLB descriptor data to load into one of the on-chip CPLB register pairs. If all on-chip registers contain valid CPLB entries, the handler selects one of the descriptors to be replaced, and the new descriptor information is loaded. Before loading new descriptor data into any CPLBs, the corresponding group of sixteen CPLBs must be disabled using:

    The Enable DCPLB (ENDCPLB) bit in the DMEM_CONTROL register for data descriptors, or

    • The Enable ICPLB (ENICPLB) bit in the IMEM_CONTROL register for instruction descriptors

     

    After the new CPLB descriptor is loaded, the exception handler returns, and the faulting memory operation is restarted. this operation should now find a valid CPLB descriptor for the requested address, and it should proceed normally.

    More details on this are given under the section "CPLB Management" of the Programming Reference Manual.

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  • 0
    •  Analog Employees 
    on Apr 6, 2009 1:06 PM

    This exception occurs because you do not have a valid CPLB entry for the region of memory that you are accessing. When the Blackfin processor issues a memory operation for which no valid CPLB (cacheability protection lookaside buffer) descriptor exists in an MMR pair, an exception occurs. This exception places the processor into Supervisor mode and vectors to the MMU exception handler.

    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.

     

     

     

     

     

    The Blackfin Programming Refernce Manual has more details on this error. The Table titled "Events That Cause Exceptions" in the chapter "Program Sequencer" gives details on the different exceptions. The type of exception caused, and the reason why it is caused can be identified by viewing the EXCAUSE field in the SEQSTAT register (Register -> Core -> Status -> Sequencer Status).

     

     

     

    From the table of EXCAUSE values, you can identify if you have got an instruction CPLB miss or a data CPLB miss. If it is an instruction CPLB miss, you can find the instruction that caused it to happen by looking at the RETX register. (Register -> Core -> Sequencer -> RETX). Also, the faulting address can be found from the I/DCPLB_STATUS registers. You can now add a CPLB entry for the region of memory that covers this faulting address.


    If you have used up all 16 CPLB entries, then you will have to dynamically manage the CPLBs to service this exception, by having a CPLB replacement policy in place. The exception handler uses the faulting address to index into the Page Descriptor Table structure to find the correct CPLB descriptor data to load into one of the on-chip CPLB register pairs. If all on-chip registers contain valid CPLB entries, the handler selects one of the descriptors to be replaced, and the new descriptor information is loaded. Before loading new descriptor data into any CPLBs, the corresponding group of sixteen CPLBs must be disabled using:

    The Enable DCPLB (ENDCPLB) bit in the DMEM_CONTROL register for data descriptors, or

    • The Enable ICPLB (ENICPLB) bit in the IMEM_CONTROL register for instruction descriptors

     

    After the new CPLB descriptor is loaded, the exception handler returns, and the faulting memory operation is restarted. this operation should now find a valid CPLB descriptor for the requested address, and it should proceed normally.

    More details on this are given under the section "CPLB Management" of the Programming Reference Manual.

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