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power up sequence in Blackfin

In my BF533 board, I used 2 seperate power supplier chips, one for 3.3V and one for 1.2V.
1.2V is available for Vint, about 3ms before 3.3V is available for Vext. Then Reset signal is provided to boot BF533, but I always found that BF533 could not give out CS signal, and could not boot from external Flash then,unless I reprovide the Reset signal(That is , at least 2 Resets are needed).
I've tried to provide 3.3V at first, then 1.2V. BF533 could boot correctly after provide one reset signal, no need to reprovide the reset signal.
I've checked all signals: RESET, NMI, BMODE0-1 using osciloscope, and there's no abvious noise, and all signals seem correct.
I saw someone has also asked similar questions on BF52X,the answers are all that there's no limitation about power provider sequence. Have someone ever provided Vint before Vext and booted successfully?

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  • Hi BobK,

    Thanks for your reply.

    1.  Customer has 10kohm resister pull-up the /BR pin to power rail  and 2kohm resister pull-down the NMI to ground .

    2.  Make all the powers stable and CLKIN stable for 1 second before /RESET is driven high, it can't work well when cusotmer uses MAX1951 as 1.2V , TPS54325 as 3.3V .

     

    3. Yes, when customer uses TPS62027 as 1.2V core power supply , all tests have show that BF533 works properly if 1.2V is on for several seconds before 3.3V is on.  I have checked TPS62207 start-up time is around 1ms,  TPS54325 is 4ms , ADP2118 is 2ms .  I don't know why TPS62207 can let BF533 work well ?

    4.  Does the BF533 always fail or just sometimes fail? --> Always fail. 

     

    5.  Can you tell how it fails?  --> BF can't boot and work well. 

    Do AMS0 and flash CE function properly after reset? --> ??

    Is there other memory on the EBIU?  --> Yes , SDRAM MT48LC8M16A2P-6A .

    Is the memory held inactive after the FPGA releases the bus?  -->Yes .

    Is there bus conflict during booting? --> FPGA will control to release bus .

     

    6.  It looks like you could easily change the sequence to VDDEXT then VDDINT by supplying 3.3V to the 1.2V regulator.  --> Yes, customer can solve it through this way. Because ADI showed that BF will not has power sequence , I don't if have another risk in this design . I shall get detail this reason to deal with the issue to further design .

     

    So the other key point is if BF need 1.2V power supply start-up time within 1ms ?

     

    Thanks a lot . 

    Angus

Reply
  • Hi BobK,

    Thanks for your reply.

    1.  Customer has 10kohm resister pull-up the /BR pin to power rail  and 2kohm resister pull-down the NMI to ground .

    2.  Make all the powers stable and CLKIN stable for 1 second before /RESET is driven high, it can't work well when cusotmer uses MAX1951 as 1.2V , TPS54325 as 3.3V .

     

    3. Yes, when customer uses TPS62027 as 1.2V core power supply , all tests have show that BF533 works properly if 1.2V is on for several seconds before 3.3V is on.  I have checked TPS62207 start-up time is around 1ms,  TPS54325 is 4ms , ADP2118 is 2ms .  I don't know why TPS62207 can let BF533 work well ?

    4.  Does the BF533 always fail or just sometimes fail? --> Always fail. 

     

    5.  Can you tell how it fails?  --> BF can't boot and work well. 

    Do AMS0 and flash CE function properly after reset? --> ??

    Is there other memory on the EBIU?  --> Yes , SDRAM MT48LC8M16A2P-6A .

    Is the memory held inactive after the FPGA releases the bus?  -->Yes .

    Is there bus conflict during booting? --> FPGA will control to release bus .

     

    6.  It looks like you could easily change the sequence to VDDEXT then VDDINT by supplying 3.3V to the 1.2V regulator.  --> Yes, customer can solve it through this way. Because ADI showed that BF will not has power sequence , I don't if have another risk in this design . I shall get detail this reason to deal with the issue to further design .

     

    So the other key point is if BF need 1.2V power supply start-up time within 1ms ?

     

    Thanks a lot . 

    Angus

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