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power up sequence in Blackfin

In my BF533 board, I used 2 seperate power supplier chips, one for 3.3V and one for 1.2V.
1.2V is available for Vint, about 3ms before 3.3V is available for Vext. Then Reset signal is provided to boot BF533, but I always found that BF533 could not give out CS signal, and could not boot from external Flash then,unless I reprovide the Reset signal(That is , at least 2 Resets are needed).
I've tried to provide 3.3V at first, then 1.2V. BF533 could boot correctly after provide one reset signal, no need to reprovide the reset signal.
I've checked all signals: RESET, NMI, BMODE0-1 using osciloscope, and there's no abvious noise, and all signals seem correct.
I saw someone has also asked similar questions on BF52X,the answers are all that there's no limitation about power provider sequence. Have someone ever provided Vint before Vext and booted successfully?

  • Hi Chen Chen,
    We believe that the BF533 should not have any power sequence requirement.  Often unconnected signals such as Bus Request can cause the behavior that you describe.  My first suggestion is to review the signals in the datasheet that must be connected to pullups or pulldowns if not used.  Another good test would be to extend the duration of the RESET.
     
    Additional hardware debug information can be found in EE-281
    Hope this helps,
    _BobK
     
     

  • Hi,

       I've checked all unused pins described in datasheet, and EE-281. All pins are connected correctly.

       Also I found that if Vint provided more than 5 ms before Vext, Blackfin could not boot correctly. While if Vint provided less than 3 ms before Vext, Blackfin could boot correctly.

       Is there any limit about the delay between Vint and Vext?

  • Hi Chen Chen,
    Thank you for checking these things because I have seen CS fail in some power configurations when BR was not connected.  I have also seen power dependent failure when NMI was not connected.
    My own testing has not shown a power sequence when switching on one supply and then seconds later switching on the other supply.  It is a surprise that 3 or 5 ms would be different.
    Other things that can prevent booting are noise and glitches on the powers.  If the VDDEXT is rising very slowly, it is susceptible to noise.  Noise on reset can be a problem and should not be generated with a simple RC circuit.  Not having a stable clock long before reset goes high could prevent startup.  Does your circuit have a crystal or an oscillator?
    There are also boot problems that are probably not related to power.  If CS to your flash is working, there could be bad data in the flash that can cause the part to fail.  One way to get past this is to set the device to another boot mode and then use the ICE to program the flash.
  • Hi,Bobk,

       Is it possible to use BF533 EZ-KIT-LITE board, to simulate different power up sequence.

  • Hi Chen Chen,
    I am not an expert on EZ-Kits but the schematic looks understandable. JP3 on page 11 selects the source of VDD_INT between the internal regulator circuit U32 or an external regulator VR6.  By removing any shunts from JP3 a lab supply could power 1.4V on pin 2 of JP3 with respect to ground before the EZ-Kit is powered on.
    If you do not have a lab supply, there is another way that requires soldering.  Remove R187 and replace it with a switch.  Supply VDD_INT my moving the jumper to pins 2 and 3 of JP3.  To get VDD_INT then VDD_EXT, power up the EZ-Kit and then turn the switch on.
    You may decide to remove Diode D4 to prevent the possibility that VDD_INT might provide power to VDD_EXT.
  • I have a customer met this issue .  Details pls find in enlcose file.

     
    BF533 design issue in one customer
     
    ADSP-BF533 is designed by one customer as DSP processor. Now customer will pilot run soon. Because customer need bigger output current for DSP system and FPGA system,   customer changed old power supply solution . Customer found DSP can’t boot well . For the detail info , you can refer below . 
     
    1.       Customer’s BF533 system
    2.       Customer’s old power supply chain
    3.       Customer’s new power supply chain
    4.       Customer’s issue
    Through customer’s test , customer found BF533 can’t boot work well when change new power supply solution.
    For the system right boot sequence, FPGA will work first . Then FPGA will release bus to BF. FPGA will send out /RESET to BF533. BF533 boot through par. FlashRom . All work ok.  Now customer found FPGA is work , but BF533 can boot right . 
    We can check the power supply system different between new power supply and old one. TPS54325 will power chain will delay 5ms work well than MAX1951. 
    5.       Customer’s test
    a.       Customer tests the timing of /RESET and power chains . Below power chain can get work well . 
    b.       Customer tests the timing of /RESET and power chains . Below power chain can’t  good work. 
    6.       Customer’s questions
    Customer wants to know if BF533’s power ( core and I/O ) has special requirements ? What’s the details ? 
     
    What's further work we can do ?
     

  • Hi Zhao,
    We have not yet seen a power sequence issue with BF533.  There are several things like /BR and NMI that can look like a power sequence issue as I have posted earlier.
    Another thing that can change with power sequence is the CLKIN startup time or the delay of reset.  To see if it helps, you could try to make all the powers stable and CLKIN stable for 1 second before /RESET is driven high.
    Your post notes that 1.2V before 3.3V works if the delay between the two is 5ms or less.  If the delay is more than 5ms, it fails.  Some tests have show that BF533 works properly if 1.2V is on for several seconds before 3.3V is on.
    Does the BF533 always fail or just sometimes fail?
    Can you tell how it fails?  Do AMS0 and flash CE function properly after reset?  Is there other memory on the EBIU?  Is the memory held inactive after the FPGA releases the bus?  Is there bus conflict during booting?
    Forgive my asking so many questions but I want to learn more about your problem.  It looks like you could easily change the sequence to VDDEXT then VDDINT by supplying 3.3V to the 1.2V regulator.  If there is a power sequence issue on the BF533, we want to learn about it quickly.
    Thanks in advance for your help.
    _BobK
  • Hi BobK,

    Thanks for your reply.

    1.  Customer has 10kohm resister pull-up the /BR pin to power rail  and 2kohm resister pull-down the NMI to ground .

    2.  Make all the powers stable and CLKIN stable for 1 second before /RESET is driven high, it can't work well when cusotmer uses MAX1951 as 1.2V , TPS54325 as 3.3V .

     

    3. Yes, when customer uses TPS62027 as 1.2V core power supply , all tests have show that BF533 works properly if 1.2V is on for several seconds before 3.3V is on.  I have checked TPS62207 start-up time is around 1ms,  TPS54325 is 4ms , ADP2118 is 2ms .  I don't know why TPS62207 can let BF533 work well ?

    4.  Does the BF533 always fail or just sometimes fail? --> Always fail. 

     

    5.  Can you tell how it fails?  --> BF can't boot and work well. 

    Do AMS0 and flash CE function properly after reset? --> ??

    Is there other memory on the EBIU?  --> Yes , SDRAM MT48LC8M16A2P-6A .

    Is the memory held inactive after the FPGA releases the bus?  -->Yes .

    Is there bus conflict during booting? --> FPGA will control to release bus .

     

    6.  It looks like you could easily change the sequence to VDDEXT then VDDINT by supplying 3.3V to the 1.2V regulator.  --> Yes, customer can solve it through this way. Because ADI showed that BF will not has power sequence , I don't if have another risk in this design . I shall get detail this reason to deal with the issue to further design .

     

    So the other key point is if BF need 1.2V power supply start-up time within 1ms ?

     

    Thanks a lot . 

    Angus

  • Thanks Angus,
    To answer your last point first, we do not know of a rise time (start up time) requirement on either VDDEXT or VDDINT.  It is important that they rise monotonically.  They should not get half way up and then fall back to zero before rising again.  Customers with very slow (40ms) rise time on VDDEXT have reported problems apparently caused by noise on VDDEXT.
    Finding the reason that the BF533 can’t boot may require measurements with a fast scope.  If you trigger the scope on reset rising, do you see AMS0 fall to enable the flash reads?  Do you see the flash data on the scope at normal levels or is there some bus contention?  Has the CLKIN been stable for a long, long time before RESET?
    If you can measure these things, it may help us understand the problem.
    _BobK
     
     
  • Hi BobK,

    I have tested below info :

    If you trigger the scope on reset rising, do you see AMS0 fall to enable the flash reads?  --> Yes.

     

     

    Do you see the flash data on the scope at normal levels or is there some bus contention?  Has the CLKIN been stable for a long, long time before RESET?

    --> All yes .

     

    I found another issue that BF533 CLKOUT pin will output 100Mhz to 300Mhz signal before reset BF533 . It is not right output .  The right output is around 66Mhz output defaultly .  Would you pls advise when BF533 confige the PLL default ?  As my idea ,  BF533 can't output right CLKOUT ( Wrong PLL default configure)  and can't boot well .

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