Post Go back to editing

UART and SPI (or mayby any two non-DMA interfaces) conflict in same Blackfin 561 core

Category: Software
Product Number: ADSP-BF561
Software Version: VisualDSP++ 5.1.2.0

I try to use two interfaces to work together: UART and SPI-slave.


For the B core, I have UART initialization:

void uart_init(unsigned int divisor)
{
packet_ready = false;

com_init(divisor);

*pILAT = *pILAT | EVT_IVG8; // clear pending IVG7 and IVG8 interrupts
*pSICB_IAR3 = Peripheral_IVG(
28,
8);


*pUART_IER = ETBEI | ERBFI;

asm("ssync;");

register_handler(
ik_ivg8,
ISR_UART_receive);

*pSICB_IMASK0 |= SIC_MASK(28);
}

For the A core, I have define-switched SPI-slave initialization:

void vovka_spi_slave_init_a(void)
{
*pSPI_CTL &= (~SPE); // disable SPI
*pSPI_STAT = TXCOL | RBSY | MODF | TXE;

*pSPI_FLG = 0;

*pSPI_BAUD = SPI_BAUD_RATE_DIVISOR;

*pSPI_CTL = CPOL | PSSE | EMISO; 

asm("ssync;");

*pSPI_CTL |= SPE; // enable SPI

register_handler(
ik_ivg11,
SPI_Interrupt);
*pSICA_IAR3 = Peripheral_IVG(
27,
11);
*pILAT |= EVT_IVG11;

asm("ssync;");

*pSICA_IMASK0 |= SIC_MASK(27);

asm("ssync;");

}

Analogously, I have define-switched SPI-slave initialization for the B core:

void spi_slave_init_b(void)
{
*pSPI_CTL &= (~SPE); // disable SPI
*pSPI_STAT = TXCOL | RBSY | MODF | TXE;

*pSPI_FLG = 0;

*pSPI_BAUD = SPI_BAUD_RATE_DIVISOR;


*pSPI_CTL = CPOL | PSSE | EMISO; 

asm("ssync;");

*pSPI_CTL |= SPE; // enable SPI

register_handler(
ik_ivg11,
SPI_Interrupt);
*pSICB_IAR3 = Peripheral_IVG(
27,
11); // DMA2 Channel 4 interrupt (SPI) 27 IVG9 27
*pILAT |= EVT_IVG11; // clear pending IVG9 interrupts

asm("ssync;");

*pSICB_IMASK0 |= SIC_MASK(27);

asm("ssync;");

}

And i see the next behavior:

  • when I switch my defines to use the A-core SPI, both UART and SPI work;
  • when I switch to the B-core SPI, UART works and SPI fails, and 
  • when I use the B-core SPI without UART setup, SPI works.

The same thing could be seen when i try to compose SPI and SPORT in one core.


What should I add/change to make UART and SPI to work in the B-core?

Or maybe there is a fundamental restriction that prevents any two non-DMI interfaces to work together in one core?