I got a query regarding asynchronous memory writes. The problem description is given below
The following are the data regarding my system
Processor - BF527
CCLK = 122.88Mhz
SCLK = 12.288MHz (CCLK/SCLK =10)
I am using an SRAM on the asynchronous memory bank 3.
The EBIU_AMBCTL1 register is programmed with the following values
B3WAT = 0xF (Write access time - 15 cycles)
B3HT = 11(Hold time - 3 cycles)
B3ST = 11(Set up time - 3 cycles)
This means that the total SCLK required for a write is(15+3+3) = 21 SCLK or 210 CCLK
Can I perform two consecutive write operation with out any delay in the above case?
Should I give a delay of 210 CCLK in between two writes ?
Will the core waits to finish a write opeartion so that the two datas are written properly to SRAM?
Please kindly help......