Delay between Asynchronous memory writes/reads

Hi,

I got a query regarding asynchronous memory writes. The problem description is given below

The following are the data regarding my system

Processor - BF527

CCLK = 122.88Mhz

SCLK = 12.288MHz (CCLK/SCLK =10)

I am using an SRAM on the asynchronous memory bank 3.

The EBIU_AMBCTL1 register is programmed with the following values

B3WAT = 0xF (Write access time - 15 cycles)

B3HT = 11(Hold time - 3 cycles)

B3ST = 11(Set up time - 3 cycles)

 

This means that the total SCLK required for a write is(15+3+3) =  21 SCLK or 210 CCLK

 

Can I perform two consecutive write operation with out any delay in the above case?

Should I give a delay of 210 CCLK in between two writes ?

Will the core waits to finish a write opeartion so that the two datas are written properly to SRAM?

 

Please kindly help......

 

Parents
  • Hi Antony,

    That is where the idea of 'interlocked-pipeline' comes from, which is a mechanism to resolve the R/W hazards. Simplest way to put it - processor pipeline is locked until data is 'actually' read from memory.

    This is also explained in the document section I mentioned earlier:-

    In the execution of instructions, the Blackfin processor architecture implements an interlocked pipeline. When a load instruction executes, the

    target register of the read operation is marked as busy until the value is returned from the memory system. If a subsequent instruction tries to

    access this register before the new value is present, the pipeline will stall until the memory operation completes. This stall guarantees that instructions

    that require the use of data resulting from the load do not use the previous or invalid data in the register, even though instructions are allowed to start execution before the memory read completes.

     

    Also the info in section 'Ordering of Loads and Stores' is very important to understand the ordering of read & write operations.

     

    Regards

    Prasanth.

     

     

     

Reply
  • Hi Antony,

    That is where the idea of 'interlocked-pipeline' comes from, which is a mechanism to resolve the R/W hazards. Simplest way to put it - processor pipeline is locked until data is 'actually' read from memory.

    This is also explained in the document section I mentioned earlier:-

    In the execution of instructions, the Blackfin processor architecture implements an interlocked pipeline. When a load instruction executes, the

    target register of the read operation is marked as busy until the value is returned from the memory system. If a subsequent instruction tries to

    access this register before the new value is present, the pipeline will stall until the memory operation completes. This stall guarantees that instructions

    that require the use of data resulting from the load do not use the previous or invalid data in the register, even though instructions are allowed to start execution before the memory read completes.

     

    Also the info in section 'Ordering of Loads and Stores' is very important to understand the ordering of read & write operations.

     

    Regards

    Prasanth.

     

     

     

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