Writing to Asynchrone memory

Hi ADI Support,

I have a problem writing and reading to the Asynch Mem bank  3. I have connected there a controller using CS#(ASM3 Select), WR#, RD# and D/C# are address lines.

I am using the following code. The first line writes a command to the controller and the second part of the code is reading from the asyn memory bank3 from the controller. This gives me always an error in reading back the result. I have noticed that the write command cycle is places inbetween the read cycle on the memory bus of the asynchronous interface. I can see this with an logic analyser that I got the write inbetween the read from the controller. Any suggestion what can cause this.

Here is a part of my code.

*pcmd_port=command; 

for(loop=0;loop<data_len;loop++)

  *data++=*pdata_port++;
}

Thanks for support

Regards

Thomas

  • Hi Thomas,

    I think your scenario has some relation to the discussion here: http://ez.analog.com/message/6146#6146

    Blackfin processors have a relaxation of synchronization between memory access instructions and their surrounding instructions, referred to as weak ordering of loads and stores. Because of weak ordering, the memory system is allowed to prioritize reads over writes. In this case, a write that is queued anywhere in the pipeline, but not completed, may be deferred by a subsequent read operation, and the read is allowed to be completed before the write.

    In an application wherein it is necessary to follow strict ordering of instructions and ensure the write occurs before reads (as per the program flow), it becomes essential to use SSYNC after the asynchronous memory/FIFO write. From your description, it would appear that a re-ordering is happening in the pipeline. The in-built compiler function is ssync() and is defined in ccblkfn.h.

    Regards

    Prasanth.

  • Hi Prasanth,

    The ssync() after write did solve the problem!

    Many thanks.

    Regards

    Thomas

  • Hi Prasanth,

    in reference to the problem with the async Memory Bank3 the first problem could be solved with the ssync().  So I have added the ssync() after each write. This works for a small amount of data. I have now a huge amount of data about 900 kByte to write and I need to write those to the asyc. memory bank 3. The controller has the characteristic to have just one address register where the data are going to be written and an internal counter that is increased for those data which are written. No I have noticed that after an undefined number the data are again swapped or some data are not written in same order or may missing. I am using the VDK project. Cache is turned off for asyc. bank3. The Bus with of the external device is 16 Bit. When I am using DMA transfer for those data to async. bank3 the data are correct written. The question is if there are some compiler direktives which are ensure that write order is garanteed and e.g. not optimized to re-order data. I have used already e.g. __builtin_aligned(a, 4) or #pragma pack(2)

     

    Any other suggestion!

     

    Regards

    Thomas

     

  • Hi Thomas,

    Sorry for this long delay.

    Is your system working fine now, or do you still have any issues with external access? When performing back-to-back write operations to external memory, you wouldn't need an ssync() in between. It shouldn't be re-ordered as it happens between read and write.

    Regards

    Prasanth.