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Powering Circuit Q's

Hello,

I am have some questions regarding the Schematics of the BF548 ezkit (attached). Specifically

the powering sections.

Firstly, a basic questions, what is the difference between the filled square and hollow

circle schematic symbol for the power buses? The page Power Page 1, for example,

on the bottom right shows the circuitry for the VDDEXT and 3.3V, shown as filled square

and hollow circle respectively. They are both 3.3V so what is the difference?

Looking now at Power Page 2, I don't really understand the power supply for VDDDR and

5V. What does the adp1823 chip setup do? I looked briefly at its datasheet but didn't

understand how it relates to the regulation of VDDDR and 5V (again the symbols are different?).

On the bottom left of this page there are two outputs for 5V_USB? Why?

Also, on the bottom right there are these symbols (MH4, MH5, etc) but they aren't connected

to anything? What are they for?

It's pretty evident there are lots of things that I'm confused with - the power circuitry has been

a bit of a hurdle. Is there an easier design for the power supply? Would really appreciate

any reference designs that have a simpler powering system.

Thanks to anyone who can be bothered to try and help. I know it is not exactly 'fun', but it

will be much appreciated.

Cheers...

A0206-2006_CUST.pdf
Parents
  • Thanks for your interest.

    Bypass Caps:

    There is no easy answer to this.  The optimum frequency for a capacitor also depends on the package size and shape.  There is a theory that if the values are close to each other, it can create a new resonant frequency resulting in more power noise.  The system design section of the HRM has a list of references.

    Series Termination:

    Impedance matching resistors at the output circuits do 3 things.  First they reduce the voltage overshoot and undershoot seen at the receiver.  This prevents long term damage to the receiver.  Secondly they reduce reflections.  Un-damped reflected waves can be seen by the receiver as false edges.  The third advantage is reduced EMI.

    PCB trace simulation of overshoot using IBIS models predicted that the BF527 required external resistors where the BF548 did not require them.

    Your maximum SDRAM equation needs some work.  Remember that not all address lines are muxed during RAS and CAS.  There are also some Bank Select lines.

    Either the internal regulator or an external regulator can be used to generate the core voltage VDDINT.  This is often chosen for cost or flexibility.  The power management section of the HRM gives more detail.

    USBRSET allows for an external correction factor that is not required for any of our current silicon.  The system design section of the HRM has more detail.

    Hope this helps.

    _BobK

Reply
  • Thanks for your interest.

    Bypass Caps:

    There is no easy answer to this.  The optimum frequency for a capacitor also depends on the package size and shape.  There is a theory that if the values are close to each other, it can create a new resonant frequency resulting in more power noise.  The system design section of the HRM has a list of references.

    Series Termination:

    Impedance matching resistors at the output circuits do 3 things.  First they reduce the voltage overshoot and undershoot seen at the receiver.  This prevents long term damage to the receiver.  Secondly they reduce reflections.  Un-damped reflected waves can be seen by the receiver as false edges.  The third advantage is reduced EMI.

    PCB trace simulation of overshoot using IBIS models predicted that the BF527 required external resistors where the BF548 did not require them.

    Your maximum SDRAM equation needs some work.  Remember that not all address lines are muxed during RAS and CAS.  There are also some Bank Select lines.

    Either the internal regulator or an external regulator can be used to generate the core voltage VDDINT.  This is often chosen for cost or flexibility.  The power management section of the HRM gives more detail.

    USBRSET allows for an external correction factor that is not required for any of our current silicon.  The system design section of the HRM has more detail.

    Hope this helps.

    _BobK

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