I'm trying to get the bf526 to talk to the AD7908 over SPI. It looks like I need CPOL = 1 and CPHA = 0, but when I choose this setting my select line stops going low when I'm trying to do a write. The 526 manual says that when CPHA = 0, the SPI slave select line is automatically controlled by hardware. Why? What line is 'the SPI hardware' supposedly driving low? What if I need these CPOL and CPHA settings but also need to be able to control which slave select line I want to pull low via the SPI flags? Can someone explain?
this bit has this dual functionality and thats how it is designed, unfortunately.
Please use e.g. the same SSEL line in GPIO mode instead.
even when PORT_FER bit is set, the following applies:
Each FLSx bit corresponds to a general purpose port pin. When an FLSx bit is set, the corresponding port pin is driven as a slave select. For example, if FLS1 is set in SPI_FLG, the port pin corresponding to SPISSEL1 is driven as a slave select.
If the FLSx bit is not set, the general-purpose port registers configure and control the corresponding port pins.
What if I am using SPISEL1? since this pin is set to SPI functionality by the MUX register at the same time as SPI CLK, MISO, and MOSI (bits 1:0 of PORTG_MUX) does that mean I have to physically modify my board so that I am using a different SPI select line in this case? One like e.g. SPISEL7 which can be configured independently?
please consider Andreas' reply a bit more. all SPISEL pins on the BF52x can operate in either GPIO or Peripheral mode. there is no hardware modification necessary to do what he suggests.
I assume you are referring to the FER register settings? Okay, that makes sense.