My board's platform is BF512F, I use the MDMA0 channel to tranfer data from L1 to asynchronous memory bank0, the EBIU_AMBCTRL0 register and the MDMA0's register are configed correctly. In my application, the asynchronous memory was a FPGA(XILINX XC3S50). The FPGA use the SCLK as it's synchromnous clock, and it will capture the bus data at the falling edge of AWE. A SDRAM chip(HY57V641620) is also used in the board. The system works well with above config. But after I changing the SDRAM chip from HY57V641620 To HY57V281620(I have changed the SDRAM's register config correctly, and the SDRAM can be access correctly), the problem happens: the MDMA0 seems to be never complete.
My question is: the SDRAM chip has an influence upon asynchronous memory's DMA ? Why the MDMA never complete after starting the MDMA's channel ?
the EBIU_AMBCTRL0 register configed as following:
SCLK = 108MHz, SETUP CYCLES = 1 Sclk, WRITE ACCESS CYCLES = 1 Sclk, ACCESS EXTEND = 0, HOLD = 0