BF512F Can't Output Correct SCLK

Hi All,

I'm using the BF512F which boots from internal SPI flash.
In the init_codes,I use the bfrom_syscontrol ROM function to config the PLL.

But some times, BF512F doesn't work after powerup, CLKOUT pin outputs a incorrect clock.

On my board one 27.0MHz oscillator drives the CLKIN pin.

The PLL programming sequence code in the init_codes is:

/*******************************************************************/
#define      SYS_MMR_BASE                 0xFFC00000

#define      IWR1_DISABLE_ALL           0x00000000      /* Wakeup Disable all peripherals */
#define      SIC_IWR1                               0xFFC00164     /* Interrupt Wakeup register */
#define      IRQ_PLL_WAKEUP             0x00000001       /* PLL Wakeup Interrupt */
#define      SIC_IWR0                               0xFFC00124     /* Interrupt Wakeup Register */

#define      IMM32(reg,val)      reg##.H=hi(val); reg##.L=lo(val)

/* Save/Restore System Interrupt Wakeup Registers */
///////////////////////////////////////////////////////////////////////////////////
#define IWR_SAVE\
        R7 = IWR1_DISABLE_ALL;\
        [P5 + lo(SIC_IWR1)] = R7;\
        R7 = IRQ_PLL_WAKEUP;\
        [P5 + lo(SIC_IWR0)] = R7

/* set Voltage Regulator and PLL Registers using the System Control ROM Function */
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

/* PLL_CTL_VAL = 0x1400 */
#define PLL_CTL_VAL             (\
                               nBYPASS              |   /* Bypass the PLL */\
                               nOUT_DELAY           |   /* Add 200ps Delay To EBIU Output Signals */\
                               nIN_DELAY            |   /* Add 200ps Delay To EBIU Input Latches */\
                               nPDWN                |   /* Enter Deep Sleep Mode */\
                               nSTOPCK              |   /* Core Clock Off */\
                               nPLL_OFF             |   /* PLL Not Powered */\
                               nDF                  |   /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */\
                                SET_MSEL(10)        |   /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */\
                                0)
       
/* PLL_DIV_VAL = 0x0004 */
#define PLL_DIV_VAL             (\
                                SET_SSEL(4)         |   /* Set SSEL = 1-15 --> SCLK = VCO/SSEL */\
                                CSEL_DIV1           |   /* CCLK = VCO / 1 */\
                                0)
       
#define PLL_LOCKCNT_VAL     0x0400
       
__full_on:

    link sizeof(ADI_SYSCTRL_VALUES)+2;
    [--SP] = (R7:0,P5:0);
    SP += -12;

    R0 = 0;
   
    R0.L = PLL_CTL_VAL;   /* 0x1400 */
    w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offsetof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R0;
   
   R0.L = PLL_LOCKCNT_VAL;  /* 0x0400 */
    w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offsetof(ADI_SYSCTRL_VALUES,uwPllLockCnt)] = R0;
   
    /* __WORKAROUND_05000432__ */
    IMM32(P3,SIC_IWR1);
    R4 = 0;
    R3 = [P3];                                    /* Save value of SIC_IWR1 */
    [P3] = R4;                                    /* Disable wakeups from SIC_IWR1 */

     /* __WORKAROUND_05000440__ */
    R0.L = PLL_DIV_VAL;
    IMM32(P5,PLL_DIV);
    w[P5] = R0;

    R0 = (SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT | SYSCTRL_WRITE );

    R1 = FP;
    R1 += -sizeof(ADI_SYSCTRL_VALUES);
    R2 = 0 (z);
    IMM32(P4,BFROM_SYSCONTROL);
    call(P4);

    [P3] = R3;                                     /* Restore original SIC_IWR1 register value */

  
    SP += 12;
    (R7:0,P5:0) = [SP++];
    unlink;
    rts;

__full_on.end:

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

_initcode:

link 0;
[--SP] = ASTAT;
[--SP] = (R7:0,P5:0);
IMM32(P5,SYS_MMR_BASE);
P4 = R0;

IWR_SAVE;

DPM:
           call __full_on;       /* set PLL Registers */

EBIU:
          call __async_mem_en;     /* FPGA */
 
SDC:
          call __sdram_en;

BMODE_SPIMEM_MODIFY_SPI_BAUD(SPI_BAUD_VAL);           /* BMODE[2:0] = 010 */

IWR_RESTORE;

(R7:0,P5:0) = [SP++];
ASTAT = [SP++];
unlink;
rts;

_initcode.end:

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

According to the above configuration, the SCLK should be:
                 SCLK = CLKIN * MSEL / SSEL = 27MHz * 10 / 4 = 67.5MHz

In my application, BF512F will output data streams to asyn memory continuously after it booted from the internal SPI flash.
It takes the DSP 10sec to boot from the flash after power-up.

Most of the time,the DSP works well,the CLKOUT pin can supply a 67.5MHz clock and the DSP can outputs correct data.
But some times after power-up, BF512F doesn't output any data, and the CLKOUT pin outputs a 18.0MHz clock.

It may work well by repower-up(needs 10 sec before output data) the DSP, or an assertion of RESET pin(less than 5 sec before output data).

I'm stucked on this problem for monthes,Could any one tell me how to fix it? Thanks.