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I2C clock stretching for BF518

Hi,

I am working on ADSP-BF518 with VDSP++5.0update8.0. I am accessing I2C RTC(DS1338) for my application and configured my SCL as 75MHz.The RTC is having 6 registers for time stamp configuration and i am writing into those registers by configuring BF518 as master. i am writing 8 bytes into RTC from BF518, but what is happening is after writing 7 bytes into slave(RTC) during the ack bit of 7 byte BF518 is stretching the clock and not releasing the bus. In the datasheet it is given that , due to FIFO underflow BF518 will stretch the clock for slave and whenever data is transfered to FIFO the bus will be released. How can we avoid this clock stretching ?

Please suggest me on this issue.

Regards,

pavan.

  • Hi Pavan,

    I’m surprised when you say SCL is 75MHz. What we support is standard(100KHz) and fast mode (max is 400KHz). Clock stretching comes into picture if the XMTSERV interrupt is not serviced. If you service this interrupt i.e. write to TWI Transmit registers is sufficient to release the clock and continue the transmission. I’ve posted couple of examples here

    Best Regards,

    Guru

  • Hi Guru,

    I am sorry for misleading you , the clock i have provided is 75KHz not 75MHz . I am not using any I2C interrupts and I am using polling mechanism in my software. considering this changes mail me your observation and suggest me any suitable example which can help me to accomplish my task.

    Thanks and Regards,

    Pavan

  • Hi Guru,

         For TWI interface I am using the same functions which are provided by analog devices.

    I am using TWI_MasterMode_Write() , TWI_MasterMode_Read() functions in my software.

    When I am writing 7 bytes into slave , stop condition is getting generated after 7th byte but

    when I am passing 8 bytes to the function TWI_MasterMode_Write() , after sending 7th byte,

    I observered clock is getting stretched and stop condition is not getting generated.

         Please support me on this issue.

    Thanks and Regards,

    Pavan

  • can you please show how you are sending the parameters to this function (when passing 7 bytes and when passing 8 bytes)...And VDSP screenshot showing TWI registers when the clock stretches?

  • Hi prasanth,

    Thank you for your response. I am using BF518 drivers provided by analog and for writing i am using TWI_MASTER_Write(TWI_SLAVE_ADDR,data_buf,1,8); and for 7 bytes i am using TWI_MASTER_Write(TWI_SLAVE_ADDR,data_buf,1,7); where data_buf[8] = {0x00,0x59,0x30,0x17,0x03,0x20,0x05,0x11}; or data_buf[8] = {0x00,0x59,0x30,0x17,0x03,0x20,0x05};

    Here first 7bytes are writing properly in to slave but during ack bit of 7th byte onwards SCL and SDA are becoming low and bus is not releasing. I can't provide VDSP screen shots but let you know the register values in my next mail. I am using 10K pull-up resistors for SCL and SDA and no series resistors to slave from processor. As per i2c specifications, for 3.3V of VDD the pull-ups for SCL and SDA must be 2.2K, it might be the reason for clock stretching?

    Pavan.

  • HI Pavan,

    I checked that function. It works fine..as expected (for both 7-byte transfer and 8-byte transfer).

    Can you please confirm whether you are using 'twi_mastermode_write' function which is also used in POST or init_code projects?

    Would it be possible for you to attach the project?

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