SMC Glue logic Parallel Interface With FPGA

Hi Shiva Chary,

Are you facing any issue while interfacing ADSP-BF609 and FPGA using SMC? Can you please elaborate your exact requirement to assist you better on this.

Regards,
Divya.P

Hi Divya,

I was Trying To Transmit Data From ADSP-BF609 To FPGA using SMC, SMC configuration have Control ,Timing, Extended Timing registers I Configured these Registers  as POST Source Code (Parallel - Flash. C)Which Is available  in CCES 1.1.0

If I Transmit Data - 0x02 on Address (SMC Bank1) 0xB4000000 From ADSP-BF609 ,

FPGA  Received as data  - 0x00  and Address - 0xFFFFFFFF 

and If I Use "unsigned int"  instead of uint32_t  for Address variable it's Giving Error like  "EXCAUSE 0x2A Exception" Why?

can You Please explain This.

Best Regards,

Shiva Chary.

Hi Divya,

-> "To Transmit Data From ADSP-BF609 To FPGA using SMC" issue was Cleared , Actually Application was Data TX/RX In Between  ADSP-BF609 To SC28L198 via FPGA  , SC28L198  was Tested With 20Mhz CLK Generated from FPGA ,7.3Mhz Crystal CLK Still SC28L198  was  Not Responding.

 SC28L198 Configuration : I configured As per Data sheet ( SC28L198) GCCR,MR0,MR1,MR2,CR,RxCSa,TxCSa,IMR Registers    

 ADSP-BF609 SMC Configuration : Ref :- POST source Code with Some Modifications In Control , Time Extended time Reg 

Control Register    : B1CTL       =  B1CTL_EN|B1CTL_Mode|B1CTL_SELCTRL;

Time Register        : B1_TIM     =  0x3F010F01;

E_Time Register   :  B1_ETIM  = 0x31311;

Address Bus : A0 - A24 ADSP-BF609 To FPGA,  A0 - A7 Connected to  SC28L198 .

Data Bus       : D0 - D15  ADSP-BF609 To FPGA , D0 - D7 Connected to  SC28L198 .

I Used Below Function to Tx Data & Address  From ADSP-BF609 To FPGA and SC28L198 

Flash_write(0xB4000000,GCCR,0x00); ,

Flash_write(0xB4000000,CR,0x00); etc...

 Flash_write(uint32_t ADDR,uint32_t ofset,uint32_t Data)

{

uint16_t *p =(uint16_t *)ADDR,res;

*(p + ofset) = Data;

SSYNC();

}

Data Transmitted From  ADSP-BF609 To FPGA & SC28L198 . SC28L198  was Not Responding 

here is FPGA  ILA Observation.

Chip Enable(TEMP3) , AWE(Write Enable) ( Data Transmits From ADSP-BF609 To SC28L198),SMC0_Bank selection.

Can Anyone Help Me With This.

Best Regards,

Shiva Chary.

Hi Divya,

-> "To Transmit Data From ADSP-BF609 To FPGA using SMC" issue was Cleared , Actually Application was Data TX/RX In Between  ADSP-BF609 To SC28L198 via FPGA  , SC28L198  was Tested With 20Mhz CLK Generated from FPGA ,7.3Mhz Crystal CLK Still SC28L198  was  Not Responding.

 SC28L198 Configuration : I configured As per Data sheet ( SC28L198) GCCR,MR0,MR1,MR2,CR,RxCSa,TxCSa,IMR Registers    

 ADSP-BF609 SMC Configuration : Ref :- POST source Code with Some Modifications In Control , Time Extended time Reg 

Control Register    : B1CTL       =  B1CTL_EN|B1CTL_Mode|B1CTL_SELCTRL;

Time Register        : B1_TIM     =  0x3F010F01;

E_Time Register   :  B1_ETIM  = 0x31311;

Address Bus : A0 - A24 ADSP-BF609 To FPGA,  A0 - A7 Connected to  SC28L198 .

Data Bus       : D0 - D15  ADSP-BF609 To FPGA , D0 - D7 Connected to  SC28L198 .

I Used Below Function to Tx Data & Address  From ADSP-BF609 To FPGA and SC28L198 

Flash_write(0xB4000000,GCCR,0x00); ,

Flash_write(0xB4000000,CR,0x00); etc...

 Flash_write(uint32_t ADDR,uint32_t ofset,uint32_t Data)

{

uint16_t *p =(uint16_t *)ADDR,res;

*(p + ofset) = Data;

SSYNC();

}

Data Transmitted From  ADSP-BF609 To FPGA & SC28L198 . SC28L198  was Not Responding 

here is FPGA  ILA Observation.

Chip Enable(TEMP3) , AWE(Write Enable) ( Data Transmits From ADSP-BF609 To SC28L198),SMC0_Bank selection.

Can Anyone Help Me With This.

Best Regards,

Shiva Chary.

Hi Shiva Chary,

While looking into your query, it seems that the similar query is handling in both private support and below Ezone thread. If you are already aware of this, please continue the discussion through private support to avoid duplication of efforts.
https://ez.analog.com/dsp/blackfin-processors/bf60x/f/q-a/574863/blackfin-glueless-interface

Regards,
Divya.P

Hi Divya,

"While looking into your query, it seems that the similar query is handling in both private support and below Ezone thread. If you are already aware of this, please continue the discussion through private support to avoid duplication of efforts."

 Sorry to say this I'm Unable connect private support.

My SMC Configuration as per Timing Characteristics only (Ref: HRM) 

TIM = 0x05130422;

ETIM = 0x00000200;

but I was getting These out put in FPGA ILA

Please Any one Help Me With this I'm Unable to Find out What Was my Mistake.

Hi Shiva Chary,

We understand that you are Tx/Rx data between ADSP-BF609 to SC28L198 via FPGA. If the clock generated from FPGA(2.MHz clock) connected to SC28L198, the data are Tx/Rx as expected. Whereas, if the SC28L198 is connected to the clock which is generated from 7.3Mhz Crystal, you are facing issue. Please correct us if our understanding is wrong.

Also, it is mentioned in the SC28L198 datasheet that "Use of a 7.3728 MHz crystal will double the Communication Clock frequencies". Could you please confirm how you are synchronizing the BF609 and SC28L198. Please let us know the clock/baud rate configuration.

Did you get a chance to refer the guidelines for configuring and enabling the SMC interface available in the ADSP-BF60x HRM manual under "SMC Programming Model" (Page No: 288/2278). Failure to follow these guidelines can lead to erroneous behavior. Please confirm whether you have followed the guidelines in your configurations.

Also, Is it possible for you to share the "SMC_GSTAT" register information of SMC.

Regards,
Divya P

Hi Divya,

The Clock is Generated from FPGA 20MHZ for SC28L198,and 7.3Mhz Crystal.

yes it is "Use of a 7.3728 MHz crystal will double the Communication Clock frequencies", Baud Rate is 115200/56700

"SMC Programming Model" (Page No: 288/2278). Failure to follow these guidelines can lead to erroneous behavior. Please confirm whether you have followed the guidelines in your configurations"

After This I was getting waveforms As per HRM.

Still, I was Unable to Communicate with Octal UART.

Blackfin CLOCKOUT =125 MHz (1 CLK Cycle is 8ns)

SMC0_MS1 is 64 ns, AWE is 32ns.

Here is My SMC_GSTAT Reg Val:

Please Help Me with This.

Thank You ,

Best Regards,

Shiva Chary.

Hi Shiva Chary,

Thanks for the update and glad to know that you are getting the waveform as per the HRM.

1) Can you please reduce the clock frequency in Blackfin and Baud Rate in the Octal UART and check whether it works.
2) Since the data transmitted from ADSP-BF609 to FPGA & SC28L198. But the SC28L198 was not responding. Could you please check the SC28L198 side. Is it possible to probe the signals in SC28L198?
3) Please check the Hardware connections between the Blackfin and Octal UART.

Regards,
Divya.P

Hi Divya,

I Did some iterations What You suggested . Still No New Updates , For this SC28L198 Side Hardware and Software Conformation, I configured  SC28L198 with FPGA (With Microblez(Softcore Processor))

FPGA and SC28L198  Communication Was Established. Octal UART Working In Between FPGA and SC28L198  I can Able to Transmit and Receive Data From/To SC28L198.

->Blackfin to FPGA (SMC Configuration Tested and Working),

->FPGA to SC28L198 (Serial Configuration Tested and Working),

" 1) Can you please reduce the clock frequency in Blackfin and Baud Rate in the Octal UART and check whether it works." Can You please Help Me with this Which Clock frequency Should I Reduce?

In SMC Clock or Blackfin Output Clock?

Can You Please Help Me With This. 

Thank You,

Best Regards,

Shiva Chary.

Hi Shiva Chary,

Thanks for confirmation.

Since the communication between Blackfin to FPGA and FPGA to SC28L198 is working as excepted, there may be a synchronization issue between BF609 and UART.

Can you please reduce the SCLK/SMC clock frequency in Blackfin and Baud Rate in the Octal UART and check.

Regards,
Divya.P

Hi,

I am Pujitha. We have also faced the same issue which got rectified by adjusting the time between successive operations.

Once upon performing a read or write operation wait for the data acknowledgement signal from SC28L198. Only upon receiving the DACKN signal perform the next read/write operation.

This has helped us to resolve the issue.